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[v2,00/12] clock: qcom: apq8084: convert to parent_data/_hws

Message ID 20230105134133.1550618-1-dmitry.baryshkov@linaro.org
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Series clock: qcom: apq8084: convert to parent_data/_hws | expand

Message

Dmitry Baryshkov Jan. 5, 2023, 1:41 p.m. UTC
Rework apq8084 gcc and mmcc drivers to use parent_data and parent_hws
instead of parent_names.

Changes since RFC:
- Fixed clock/clock-names's maxItems in qcom,mmcc.yaml
- Expanded qcom,gcc-apq8084 example to include an example of UFS symbol
  clock bindings

Dmitry Baryshkov (12):
  dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names
  dt-bindings: clock: qcom,gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC
  dt-bindings: clock: qcom,mmcc: define clocks/clock-names for APQ8084
  clk: qcom: gcc-apq8084: use ARRAY_SIZE instead of specifying
    num_parents
  clk: qcom: gcc-apq8084: move PLL clocks up
  clk: qcom: gcc-apq8084: use parent_hws/_data instead of parent_names
  clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC
  clk: qcom: mmcc-apq8084: use ARRAY_SIZE instead of specifying
    num_parents
  clk: qcom: mmcc-apq8084: move clock parent tables down
  clk: qcom: mmcc-apq8084: remove spdm clocks
  clk: qcom: mmcc-apq8084: use parent_hws/_data instead of parent_names
  ARM: dts: qcom: apq8084: add clocks and clock-names to gcc device

 .../bindings/clock/qcom,gcc-apq8084.yaml      |   48 +
 .../devicetree/bindings/clock/qcom,mmcc.yaml  |   44 +-
 arch/arm/boot/dts/qcom-apq8084.dtsi           |   18 +
 drivers/clk/qcom/gcc-apq8084.c                | 1024 +++++++-------
 drivers/clk/qcom/mmcc-apq8084.c               | 1189 +++++++----------
 include/dt-bindings/clock/qcom,gcc-apq8084.h  |    1 +
 6 files changed, 1102 insertions(+), 1222 deletions(-)

Comments

Krzysztof Kozlowski Jan. 6, 2023, 12:50 p.m. UTC | #1
On 05/01/2023 14:41, Dmitry Baryshkov wrote:
> Define clock/clock-names properties of the GCC device node to be used
> on APQ8084 platform.
> 
> Note: the driver uses a single pcie_pipe clock, however most probably
> there are two pipe clocks, one from each of PCIe QMP PHYs.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../bindings/clock/qcom,gcc-apq8084.yaml      | 48 +++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
> index 8ade176c24f4..732b6770b46e 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
> @@ -25,6 +25,30 @@ properties:
>    compatible:
>      const: qcom,gcc-apq8084
>  
> +  clocks:
> +    items:
> +      - description: XO source
> +      - description: Sleep clock source
> +      - description: UFS RX symbol 0 clock
> +      - description: UFS RX symbol 1 clock
> +      - description: UFS TX symbol 0 clock
> +      - description: UFS TX symbol 1 clock
> +      - description: SATA ASIC0 clock
> +      - description: SATA RX clock
> +      - description: PCIe PIPE clock
> +
> +  clock-names:
> +    items:
> +      - const: xo
> +      - const: sleep_clk
> +      - const: ufs_rx_symbol_0_clk_src
> +      - const: ufs_rx_symbol_1_clk_src
> +      - const: ufs_tx_symbol_0_clk_src
> +      - const: ufs_tx_symbol_1_clk_src
> +      - const: sata_asic0_clk
> +      - const: sata_rx_clk
> +      - const: pcie_pipe
> +
>  required:
>    - compatible
>  
> @@ -32,11 +56,35 @@ unevaluatedProperties: false
>  
>  examples:
>    - |
> +    /* UFS PHY on APQ8084 is not supported (yet), so these bindings just serve an example */
> +    #define UFS_PHY_RX_SYMBOL_0 0
> +    #define UFS_PHY_RX_SYMBOL_1 1
> +    #define UFS_PHY_TX_SYMBOL_0 2

Use numbers in example instead.


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof