| Message ID | 20221231233851.24923-1-samuel@sholland.org |
|---|---|
| Headers | show |
| Series | riscv: Allwinner D1/D1s platform support | expand |
On Sat, 31 Dec 2022 17:38:43 -0600 Samuel Holland <samuel@sholland.org> wrote: Hi, > D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based > on a single die, or at a pair of dies derived from the same design. > > D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and > T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of > the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP > variants. > > Because the original design supported both ARM and RISC-V CPUs, some > peripherals are duplicated. In addition, all variants except D1s contain > a HiFi 4 DSP with its own set of peripherals. > > The devicetrees are organized to minimize duplication: > - Common perhiperals are described in sunxi-d1s-t113.dtsi > - DSP-related peripherals are described in sunxi-d1-t113.dtsi > - RISC-V specific hardware is described in sun20i-d1s.dtsi > - Functionality unique to the D1 variant is described in sun20i-d1.dtsi > > The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells > values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC. I compared to the v2 post (which I already checked against the T113-s manual) and did not find any extra changes apart from those mentioned in the changelog below. As my two questions from v2 are answered: Reviewed-by: Andre Przywara <andre.przywara@arm.com> Many thanks, Andre > > Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu> > Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu> > Signed-off-by: Samuel Holland <samuel@sholland.org> > --- > > (no changes since v3) > > Changes in v3: > - Drop dummy DCXO clock-frequency property > - Decrease the PLIC's riscv,ndev property to 175 > - Fix `make W=1 dtbs` warnings (unnecessary #address/#size-cells) > > Changes in v2: > - Split into separate files for sharing with D1s/R528/T113 > - Use SOC_PERIPHERAL_IRQ macro for interrupts > - Rename osc24M to dcxo and move the frequency to the board DTs > - Drop analog LDOs due to the missing binding > - Correct tcon_top DSI clock reference > - Add DMIC, DSI controller, and DPHY (bindings are in linux-next) > - Add CPU OPP table > > arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 66 ++ > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 76 ++ > .../boot/dts/allwinner/sunxi-d1-t113.dtsi | 15 + > .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 837 ++++++++++++++++++ > 4 files changed, 994 insertions(+) > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi > create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > ...