| Message ID | 20221227013225.2847382-1-dmitry.baryshkov@linaro.org |
|---|---|
| Headers | show |
| Series | clock: qcom: apq8084: convert to parent_data/_hws | expand |
On 28/12/2022 12:30, Krzysztof Kozlowski wrote: > On 27/12/2022 02:32, Dmitry Baryshkov wrote: >> Define clock/clock-names properties of the GCC device node to be used >> on APQ8084 platform. >> >> Note: the driver uses a single pcie_pipe clock, however most probably >> there are two pipe clocks, one from each of PCIe QMP PHYs. >> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- >> .../bindings/clock/qcom,gcc-apq8084.yaml | 43 +++++++++++++++++++ >> 1 file changed, 43 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml >> index 8ade176c24f4..02a856f14fbe 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml >> @@ -25,6 +25,30 @@ properties: >> compatible: >> const: qcom,gcc-apq8084 >> >> + clocks: >> + items: >> + - description: XO source >> + - description: Sleep clock source >> + - description: UFS RX symbol 0 clock >> + - description: UFS RX symbol 1 clock >> + - description: UFS TX symbol 0 clock >> + - description: UFS TX symbol 1 clock >> + - description: SATA ASIC0 clock >> + - description: SATA RX clock >> + - description: PCIe PIPE clock >> + >> + clock-names: >> + items: >> + - const: xo >> + - const: sleep_clk >> + - const: ufs_rx_symbol_0_clk_src >> + - const: ufs_rx_symbol_1_clk_src >> + - const: ufs_tx_symbol_0_clk_src >> + - const: ufs_tx_symbol_1_clk_src >> + - const: sata_asic0_clk >> + - const: sata_rx_clk >> + - const: pcie_pipe >> + >> required: >> - compatible >> >> @@ -38,5 +62,24 @@ examples: >> #clock-cells = <1>; >> #reset-cells = <1>; >> #power-domain-cells = <1>; >> + >> + clocks = <&xo_board>, >> + <&sleep_clk>, >> + <&ufsphy 0>, > > No IDs available yet? No. I didn't add IDs to the UFS symbol patchset. And anyway apq8084 seems to use different amount of UFS symbol clocks (4, while other platforms use just 3).
Rework apq8084 gcc and mmcc drivers to use parent_data and parent_hws instead of parent_names. The series is sent as an RFC, since some of the parents are not fully clear to me. Dmitry Baryshkov (12): dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names dt-bindings: clock: qcom,gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC dt-bindings: clock: qcom,mmcc: define clocks/clock-names for APQ8084 clk: qcom: gcc-apq8084: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-apq8084: move PLL clocks up clk: qcom: gcc-apq8084: use parent_hws/_data instead of parent_names clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC clk: qcom: mmcc-apq8084: use ARRAY_SIZE instead of specifying num_parents clk: qcom: mmcc-apq8084: move clock parent tables down clk: qcom: mmcc-apq8084: remove spdm clocks clk: qcom: mmcc-apq8084: use parent_hws/_data instead of parent_names ARM: dts: qcom: apq8084: add clocks and clock-names to gcc device .../bindings/clock/qcom,gcc-apq8084.yaml | 43 + .../devicetree/bindings/clock/qcom,mmcc.yaml | 40 + arch/arm/boot/dts/qcom-apq8084.dtsi | 18 + drivers/clk/qcom/gcc-apq8084.c | 1024 +++++++------- drivers/clk/qcom/mmcc-apq8084.c | 1189 +++++++---------- include/dt-bindings/clock/qcom,gcc-apq8084.h | 1 + 6 files changed, 1095 insertions(+), 1220 deletions(-)