| Message ID | 20221212123311.146261-8-manivannan.sadhasivam@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Qcom: LLCC/EDAC: Fix base address used for LLCC banks | expand |
On 12/12/2022 6:03 PM, Manivannan Sadhasivam wrote: > The LLCC block has several banks each with a different base address > and holes in between. So it is not a correct approach to cover these > banks with a single offset/size. Instead, the individual bank's base > address needs to be specified in devicetree with the exact size. > > Also, let's get rid of reg-names property as it is not needed anymore. > The driver is expected to parse the reg field based on index to get the > addresses of each LLCC banks. > > Cc: <stable@vger.kernel.org> # 5.11 > Fixes: bb1f7cf68a2d ("arm64: dts: qcom: sm8150: Add LLC support for sm8150") > Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8150.dtsi | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > index a0c57fb798d3..958655bf5b1a 100644 > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > @@ -1762,8 +1762,9 @@ mmss_noc: interconnect@1740000 { > > system-cache-controller@9200000 { > compatible = "qcom,sm8150-llcc"; > - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; > - reg-names = "llcc_base", "llcc_broadcast_base"; > + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, > + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, > + <0 0x09600000 0 0x50000>; > interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; > }; > Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a0c57fb798d3..958655bf5b1a 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1762,8 +1762,9 @@ mmss_noc: interconnect@1740000 { system-cache-controller@9200000 { compatible = "qcom,sm8150-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; };
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: <stable@vger.kernel.org> # 5.11 Fixes: bb1f7cf68a2d ("arm64: dts: qcom: sm8150: Add LLC support for sm8150") Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)