| Message ID | 20221215174013.1003508-1-peter.maydell@linaro.org |
|---|---|
| State | Not Applicable |
| Headers | show |
On Thu, 15 Dec 2022 at 17:40, Peter Maydell <peter.maydell@linaro.org> wrote: > > drop the sysregs patch as the tcg sysregs test fails > (probably a bug in the test) > > -- PMM > > The following changes since commit ae2b87341b5ddb0dcb1b3f2d4f586ef18de75873: > > Merge tag 'pull-qapi-2022-12-14-v2' of https://repo.or.cz/qemu/armbru into staging (2022-12-14 22:42:14 +0000) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221215-1 > > for you to fetch changes up to 9e406eea309bbe44c7fb17f6af112d2b756854ad: > > target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator (2022-12-15 17:37:48 +0000) > > ---------------------------------------------------------------- > target-arm queue: > * hw/arm/virt: Add properties to allow more granular > configuration of use of highmem space > * target/arm: Add Cortex-A55 CPU > * hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement > * Implement FEAT_EVT > * Some 3-phase-reset conversions for Arm GIC, SMMU > * hw/arm/boot: set initrd with #address-cells type in fdt > * hw/misc: Move some arm-related files from specific_ss into softmmu_ss > * Restrict arm_cpu_exec_interrupt() to TCG accelerator Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0 for any user-visible changes. -- PMM
Peter Maydell <peter.maydell@linaro.org> writes: > drop the sysregs patch as the tcg sysregs test fails > (probably a bug in the test) Well I assume because it complains about extra bits leaking into userspace: ➜ ./qemu-aarch64 ./tests/tcg/aarch64-linux-user/sysregs Checking Counter registers ctr_el0 : 0x0000000080038003 cntvct_el0 : 0x017314376c668b73 cntfrq_el0 : 0x0000000003b9aca0 Checking CPUID registers id_aa64isar0_el1 : 0x1021111110212120 !!extra bits!! : 0x1000000000000000 id_aa64isar1_el1 : 0x0011101101211012 !!extra bits!! : 0x0011100100000000 id_aa64mmfr0_el1 : 0xffffffffff000000 !!extra bits!! : 0xffffffff00000000 id_aa64pfr0_el1 : 0x0001000100110011 id_aa64pfr1_el1 : 0x0000000001000321 !!extra bits!! : 0x0000000001000301 id_aa64dfr0_el1 : 0x0000000000000006 id_aa64zfr0_el1 : 0x0110110100110021 (not RAZ!) midr_el1 : 0x00000000000f0510 mpidr_el1 : 0x0000000080000000 Remaining registers should fail id_mmfr0_el1 : 0x00000000deadbeef id_mmfr1_el1 : 0x00000000deadbeef id_mmfr2_el1 : 0x00000000deadbeef id_mmfr3_el1 : 0x00000000deadbeef mvfr0_el1 : 0x00000000deadbeef mvfr1_el1 : 0x00000000deadbeef Extra information leaked to user-space! So it should have been updated when the API was changed. > > -- PMM > > The following changes since commit ae2b87341b5ddb0dcb1b3f2d4f586ef18de75873: > > Merge tag 'pull-qapi-2022-12-14-v2' of https://repo.or.cz/qemu/armbru into staging (2022-12-14 22:42:14 +0000) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221215-1 > > for you to fetch changes up to 9e406eea309bbe44c7fb17f6af112d2b756854ad: > > target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator (2022-12-15 17:37:48 +0000) > > ---------------------------------------------------------------- > target-arm queue: > * hw/arm/virt: Add properties to allow more granular > configuration of use of highmem space > * target/arm: Add Cortex-A55 CPU > * hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement > * Implement FEAT_EVT > * Some 3-phase-reset conversions for Arm GIC, SMMU > * hw/arm/boot: set initrd with #address-cells type in fdt > * hw/misc: Move some arm-related files from specific_ss into softmmu_ss > * Restrict arm_cpu_exec_interrupt() to TCG accelerator > > ---------------------------------------------------------------- > Gavin Shan (7): > hw/arm/virt: Introduce virt_set_high_memmap() helper > hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap() > hw/arm/virt: Introduce variable region_base in virt_set_high_memmap() > hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper > hw/arm/virt: Improve high memory region address assignment > hw/arm/virt: Add 'compact-highmem' property > hw/arm/virt: Add properties to disable high memory regions > > Luke Starrett (1): > hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement > > Mihai Carabas (1): > hw/arm/virt: build SMBIOS 19 table > > Peter Maydell (15): > target/arm: Allow relevant HCR bits to be written for FEAT_EVT > target/arm: Implement HCR_EL2.TTLBIS traps > target/arm: Implement HCR_EL2.TTLBOS traps > target/arm: Implement HCR_EL2.TICAB,TOCU traps > target/arm: Implement HCR_EL2.TID4 traps > target/arm: Report FEAT_EVT for TCG '-cpu max' > hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset > hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset > hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset > hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset > hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset > hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset > hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset > hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset > hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset > > Philippe Mathieu-Daudé (1): > target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator > > Schspa Shi (1): > hw/arm/boot: set initrd with #address-cells type in fdt > > Thomas Huth (1): > hw/misc: Move some arm-related files from specific_ss into softmmu_ss > > Timofey Kutergin (1): > target/arm: Add Cortex-A55 CPU > > docs/system/arm/emulation.rst | 1 + > docs/system/arm/virt.rst | 18 +++ > include/hw/arm/smmuv3.h | 2 +- > include/hw/arm/virt.h | 2 + > include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 2 +- > target/arm/cpu.h | 30 +++++ > target/arm/kvm-consts.h | 8 +- > hw/arm/boot.c | 10 +- > hw/arm/smmu-common.c | 7 +- > hw/arm/smmuv3.c | 12 +- > hw/arm/virt.c | 202 +++++++++++++++++++++++++++------ > hw/intc/arm_gic_common.c | 7 +- > hw/intc/arm_gic_kvm.c | 14 ++- > hw/intc/arm_gicv3_common.c | 7 +- > hw/intc/arm_gicv3_dist.c | 4 +- > hw/intc/arm_gicv3_its.c | 14 ++- > hw/intc/arm_gicv3_its_common.c | 7 +- > hw/intc/arm_gicv3_its_kvm.c | 14 ++- > hw/intc/arm_gicv3_kvm.c | 14 ++- > hw/misc/imx6_src.c | 2 +- > hw/misc/iotkit-sysctl.c | 1 - > target/arm/cpu.c | 5 +- > target/arm/cpu64.c | 70 ++++++++++++ > target/arm/cpu_tcg.c | 1 + > target/arm/helper.c | 135 ++++++++++++++-------- > hw/misc/meson.build | 11 +- > 26 files changed, 459 insertions(+), 141 deletions(-)
On Fri, 16 Dec 2022 at 11:49, Alex Bennée <alex.bennee@linaro.org> wrote: > > > Peter Maydell <peter.maydell@linaro.org> writes: > > > drop the sysregs patch as the tcg sysregs test fails > > (probably a bug in the test) > > Well I assume because it complains about extra bits leaking into > userspace: > > ➜ ./qemu-aarch64 ./tests/tcg/aarch64-linux-user/sysregs > Checking Counter registers > ctr_el0 : 0x0000000080038003 > cntvct_el0 : 0x017314376c668b73 > cntfrq_el0 : 0x0000000003b9aca0 > Checking CPUID registers > id_aa64isar0_el1 : 0x1021111110212120 > !!extra bits!! : 0x1000000000000000 > id_aa64isar1_el1 : 0x0011101101211012 > !!extra bits!! : 0x0011100100000000 > id_aa64mmfr0_el1 : 0xffffffffff000000 > !!extra bits!! : 0xffffffff00000000 > id_aa64pfr0_el1 : 0x0001000100110011 > id_aa64pfr1_el1 : 0x0000000001000321 > !!extra bits!! : 0x0000000001000301 > id_aa64dfr0_el1 : 0x0000000000000006 > id_aa64zfr0_el1 : 0x0110110100110021 (not RAZ!) > midr_el1 : 0x00000000000f0510 > mpidr_el1 : 0x0000000080000000 > Remaining registers should fail > id_mmfr0_el1 : 0x00000000deadbeef > id_mmfr1_el1 : 0x00000000deadbeef > id_mmfr2_el1 : 0x00000000deadbeef > id_mmfr3_el1 : 0x00000000deadbeef > mvfr0_el1 : 0x00000000deadbeef > mvfr1_el1 : 0x00000000deadbeef > Extra information leaked to user-space! > > So it should have been updated when the API was changed. Yes, exactly (or written in a way that supports "in future we might expose more fields"). thanks -- PMM
drop the sysregs patch as the tcg sysregs test fails (probably a bug in the test) -- PMM The following changes since commit ae2b87341b5ddb0dcb1b3f2d4f586ef18de75873: Merge tag 'pull-qapi-2022-12-14-v2' of https://repo.or.cz/qemu/armbru into staging (2022-12-14 22:42:14 +0000) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221215-1 for you to fetch changes up to 9e406eea309bbe44c7fb17f6af112d2b756854ad: target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator (2022-12-15 17:37:48 +0000) ---------------------------------------------------------------- target-arm queue: * hw/arm/virt: Add properties to allow more granular configuration of use of highmem space * target/arm: Add Cortex-A55 CPU * hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement * Implement FEAT_EVT * Some 3-phase-reset conversions for Arm GIC, SMMU * hw/arm/boot: set initrd with #address-cells type in fdt * hw/misc: Move some arm-related files from specific_ss into softmmu_ss * Restrict arm_cpu_exec_interrupt() to TCG accelerator ---------------------------------------------------------------- Gavin Shan (7): hw/arm/virt: Introduce virt_set_high_memmap() helper hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap() hw/arm/virt: Introduce variable region_base in virt_set_high_memmap() hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper hw/arm/virt: Improve high memory region address assignment hw/arm/virt: Add 'compact-highmem' property hw/arm/virt: Add properties to disable high memory regions Luke Starrett (1): hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement Mihai Carabas (1): hw/arm/virt: build SMBIOS 19 table Peter Maydell (15): target/arm: Allow relevant HCR bits to be written for FEAT_EVT target/arm: Implement HCR_EL2.TTLBIS traps target/arm: Implement HCR_EL2.TTLBOS traps target/arm: Implement HCR_EL2.TICAB,TOCU traps target/arm: Implement HCR_EL2.TID4 traps target/arm: Report FEAT_EVT for TCG '-cpu max' hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset Philippe Mathieu-Daudé (1): target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator Schspa Shi (1): hw/arm/boot: set initrd with #address-cells type in fdt Thomas Huth (1): hw/misc: Move some arm-related files from specific_ss into softmmu_ss Timofey Kutergin (1): target/arm: Add Cortex-A55 CPU docs/system/arm/emulation.rst | 1 + docs/system/arm/virt.rst | 18 +++ include/hw/arm/smmuv3.h | 2 +- include/hw/arm/virt.h | 2 + include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 2 +- target/arm/cpu.h | 30 +++++ target/arm/kvm-consts.h | 8 +- hw/arm/boot.c | 10 +- hw/arm/smmu-common.c | 7 +- hw/arm/smmuv3.c | 12 +- hw/arm/virt.c | 202 +++++++++++++++++++++++++++------ hw/intc/arm_gic_common.c | 7 +- hw/intc/arm_gic_kvm.c | 14 ++- hw/intc/arm_gicv3_common.c | 7 +- hw/intc/arm_gicv3_dist.c | 4 +- hw/intc/arm_gicv3_its.c | 14 ++- hw/intc/arm_gicv3_its_common.c | 7 +- hw/intc/arm_gicv3_its_kvm.c | 14 ++- hw/intc/arm_gicv3_kvm.c | 14 ++- hw/misc/imx6_src.c | 2 +- hw/misc/iotkit-sysctl.c | 1 - target/arm/cpu.c | 5 +- target/arm/cpu64.c | 70 ++++++++++++ target/arm/cpu_tcg.c | 1 + target/arm/helper.c | 135 ++++++++++++++-------- hw/misc/meson.build | 11 +- 26 files changed, 459 insertions(+), 141 deletions(-)