| Message ID | 20221115152727.9736-2-konrad.dybcio@linaro.org |
|---|---|
| State | Accepted |
| Commit | 6bc6af375c7025663fbc36bcb7e91f3af653742b |
| Headers | show |
| Series | SM6375/PDX225 GPI DMA, QUPs & PMIC peripherals | expand |
On Fri, Nov 18, 2022 at 01:38:56PM +0000, Will Deacon wrote: > On Tue, Nov 15, 2022 at 04:27:19PM +0100, Konrad Dybcio wrote: > > The SMMU on SM6375 requires 3 power domains to be active. Add an > > appropriate description of that. > > > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > --- > > .../devicetree/bindings/iommu/arm,smmu.yaml | 23 ++++++++++++++++++- > > 1 file changed, 22 insertions(+), 1 deletion(-) > > Acked-by: Will Deacon <will@kernel.org> > > Let me know if you'd like me to take this one via the Arm SMMU tree. > Yes, please pick this through the SMMU tree. Bjorn
Hi Bjorn, On Mon, Dec 05, 2022 at 02:56:40PM -0600, Bjorn Andersson wrote: > On Fri, Nov 18, 2022 at 01:38:56PM +0000, Will Deacon wrote: > > On Tue, Nov 15, 2022 at 04:27:19PM +0100, Konrad Dybcio wrote: > > > The SMMU on SM6375 requires 3 power domains to be active. Add an > > > appropriate description of that. > > > > > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > > --- > > > .../devicetree/bindings/iommu/arm,smmu.yaml | 23 ++++++++++++++++++- > > > 1 file changed, 22 insertions(+), 1 deletion(-) > > > > Acked-by: Will Deacon <will@kernel.org> > > > > Let me know if you'd like me to take this one via the Arm SMMU tree. > > > > Yes, please pick this through the SMMU tree. I've already sent my pull request for 6.2, so this will have to wait until 6.3 now (unless somebody else takes it in the meantime). Will
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 28f5720824cd..348a73f3e5f0 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -200,7 +200,8 @@ properties: maxItems: 7 power-domains: - maxItems: 1 + minItems: 1 + maxItems: 3 nvidia,memory-controller: description: | @@ -364,6 +365,26 @@ allOf: - description: interface clock required to access smmu's registers through the TCU's programming interface. + - if: + properties: + compatible: + contains: + const: qcom,sm6375-smmu-500 + then: + properties: + power-domains: + items: + - description: SNoC MMU TBU RT GDSC + - description: SNoC MMU TBU NRT GDSC + - description: SNoC TURING MMU TBU0 GDSC + + required: + - power-domains + else: + properties: + power-domains: + maxItems: 1 + examples: - |+ /* SMMU with stream matching or stream indexing */
The SMMU on SM6375 requires 3 power domains to be active. Add an appropriate description of that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- .../devicetree/bindings/iommu/arm,smmu.yaml | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-)