| Message ID | 20221124115023.2437291-18-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Convert most CPU classes to 3-phase reset | expand |
On 24/11/2022 11:50, Peter Maydell wrote: > Convert the sparc CPU class to use 3-phase reset, so it doesn't > need to use device_class_set_parent_reset() any more. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/sparc/cpu-qom.h | 4 ++-- > target/sparc/cpu.c | 12 ++++++++---- > 2 files changed, 10 insertions(+), 6 deletions(-) > > diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h > index 86ed37d9333..78bf00b9a23 100644 > --- a/target/sparc/cpu-qom.h > +++ b/target/sparc/cpu-qom.h > @@ -35,7 +35,7 @@ typedef struct sparc_def_t sparc_def_t; > /** > * SPARCCPUClass: > * @parent_realize: The parent class' realize handler. > - * @parent_reset: The parent class' reset handler. > + * @parent_phases: The parent class' reset phase handlers. > * > * A SPARC CPU model. > */ > @@ -45,7 +45,7 @@ struct SPARCCPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - DeviceReset parent_reset; > + ResettablePhases parent_phases; > sparc_def_t *cpu_def; > }; > > diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c > index 4c3d08a8751..1734ef8dc6b 100644 > --- a/target/sparc/cpu.c > +++ b/target/sparc/cpu.c > @@ -28,14 +28,16 @@ > > //#define DEBUG_FEATURES > > -static void sparc_cpu_reset(DeviceState *dev) > +static void sparc_cpu_reset_hold(Object *obj) > { > - CPUState *s = CPU(dev); > + CPUState *s = CPU(obj); > SPARCCPU *cpu = SPARC_CPU(s); > SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu); > CPUSPARCState *env = &cpu->env; > > - scc->parent_reset(dev); > + if (scc->parent_phases.hold) { > + scc->parent_phases.hold(obj); > + } > > memset(env, 0, offsetof(CPUSPARCState, end_reset_fields)); > env->cwp = 0; > @@ -889,12 +891,14 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) > SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); > CPUClass *cc = CPU_CLASS(oc); > DeviceClass *dc = DEVICE_CLASS(oc); > + ResettableClass *rc = RESETTABLE_CLASS(oc); > > device_class_set_parent_realize(dc, sparc_cpu_realizefn, > &scc->parent_realize); > device_class_set_props(dc, sparc_cpu_properties); > > - device_class_set_parent_reset(dc, sparc_cpu_reset, &scc->parent_reset); > + resettable_class_set_parent_phases(rc, NULL, sparc_cpu_reset_hold, NULL, > + &scc->parent_phases); > > cc->class_by_name = sparc_cpu_class_by_name; > cc->parse_features = sparc_cpu_parse_features; Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> ATB, Mark.
diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h index 86ed37d9333..78bf00b9a23 100644 --- a/target/sparc/cpu-qom.h +++ b/target/sparc/cpu-qom.h @@ -35,7 +35,7 @@ typedef struct sparc_def_t sparc_def_t; /** * SPARCCPUClass: * @parent_realize: The parent class' realize handler. - * @parent_reset: The parent class' reset handler. + * @parent_phases: The parent class' reset phase handlers. * * A SPARC CPU model. */ @@ -45,7 +45,7 @@ struct SPARCCPUClass { /*< public >*/ DeviceRealize parent_realize; - DeviceReset parent_reset; + ResettablePhases parent_phases; sparc_def_t *cpu_def; }; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 4c3d08a8751..1734ef8dc6b 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -28,14 +28,16 @@ //#define DEBUG_FEATURES -static void sparc_cpu_reset(DeviceState *dev) +static void sparc_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(dev); + CPUState *s = CPU(obj); SPARCCPU *cpu = SPARC_CPU(s); SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu); CPUSPARCState *env = &cpu->env; - scc->parent_reset(dev); + if (scc->parent_phases.hold) { + scc->parent_phases.hold(obj); + } memset(env, 0, offsetof(CPUSPARCState, end_reset_fields)); env->cwp = 0; @@ -889,12 +891,14 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); device_class_set_parent_realize(dc, sparc_cpu_realizefn, &scc->parent_realize); device_class_set_props(dc, sparc_cpu_properties); - device_class_set_parent_reset(dc, sparc_cpu_reset, &scc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, sparc_cpu_reset_hold, NULL, + &scc->parent_phases); cc->class_by_name = sparc_cpu_class_by_name; cc->parse_features = sparc_cpu_parse_features;
Convert the sparc CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/sparc/cpu-qom.h | 4 ++-- target/sparc/cpu.c | 12 ++++++++---- 2 files changed, 10 insertions(+), 6 deletions(-)