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[v8,0/4] phy: qcom-qmp-ufs: add symbol clocks support

Message ID 20221123104215.3414528-1-dmitry.baryshkov@linaro.org
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Series phy: qcom-qmp-ufs: add symbol clocks support | expand

Message

Dmitry Baryshkov Nov. 23, 2022, 10:42 a.m. UTC 
Register UFS symbol clocks in the Qualcomm QMP PHY driver. Some of the
platforms (msm8996, sc7280, sm8350/sm8450) expect them to be defined (to
be used as GCC clock parents).

Changes since v7:
- Rebased on top of phy/next
- Renamed the clock registration function (Johan)
- Dropped rogue qcom_qmp_ufs_ops (Johan)
- Fixed the comment following Johan's suggestion.

Changes since v6:
- Added bindings change (Johan, thanks for the reminder)
- Added corresponding dts changes for msm8996 and sm8350/sm8450.

Changes since v5:
- Rebased on top of phy/next

Changes since v4:
- Rebased, dropping merged clk patches
- Fixed whitespace errors
- Added linebreaks to fit into 100 chars limit

Changes since v3:
- Rewrote asm9260 clk driver to fix the TODO item by using parent index
  rather than calling of_clk_get_parent_name().

Changes since v2:
- Added error handling to phy_symbols_clk_register() (requested by
  Johan).

Changes since v1:
- Added a macro used by clk-asm9260, so that the clk-fixed-rate changes
  do not affect the driver
- Changed registered clock names to be unique (as e.g. SC8280XP will
  have two UFS PHYs).


Dmitry Baryshkov (2):
  dt-bindings: phy: qcom,*-qmp-ufs-phy: add clock-cells property
  phy: qcom-qmp-ufs: provide symbol clocks

Yoshihiro Shimoda (2):
  dt-bindings: phy: renesas: Document Renesas Ethernet SERDES
  phy: renesas: Add Renesas Ethernet SERDES driver for R-Car S4-8

 .../phy/qcom,msm8996-qmp-ufs-phy.yaml         |   3 +
 .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml        |   3 +
 .../phy/renesas,r8a779f0-ether-serdes.yaml    |  54 +++
 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c       |  64 +++
 drivers/phy/renesas/Kconfig                   |   8 +
 drivers/phy/renesas/Makefile                  |   1 +
 drivers/phy/renesas/r8a779f0-ether-serdes.c   | 417 ++++++++++++++++++
 7 files changed, 550 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/renesas,r8a779f0-ether-serdes.yaml
 create mode 100644 drivers/phy/renesas/r8a779f0-ether-serdes.c

Comments

Dmitry Baryshkov Nov. 23, 2022, 10:43 a.m. UTC | #1 
On 23/11/2022 12:42, Dmitry Baryshkov wrote:
> Register UFS symbol clocks in the Qualcomm QMP PHY driver. Some of the
> platforms (msm8996, sc7280, sm8350/sm8450) expect them to be defined (to
> be used as GCC clock parents).
> 
> Changes since v7:
> - Rebased on top of phy/next
> - Renamed the clock registration function (Johan)
> - Dropped rogue qcom_qmp_ufs_ops (Johan)
> - Fixed the comment following Johan's suggestion.
Ugh, this went total crazy with me sending the patches from the wrong 
commit. Please excuse me, I'll send v9 instead.