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[v4,0/2] clk: qcom: Add clocks for the QDU1000 and QRU1000 SoC

Message ID 20221118181826.28269-1-quic_molvera@quicinc.com
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Series clk: qcom: Add clocks for the QDU1000 and QRU1000 SoC | expand

Message

Melody Olvera Nov. 18, 2022, 6:18 p.m. UTC
This series adds the GCC, RPMh, and PDC clock support required for the
QDU1000 and QRU1000 SoCs along with the devicetree bindings for them.

The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit
1000 are new SoCs meant for enabling Open RAN solutions. See more at
https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf

Changes from v3:
- added example sources for PCIE and USB clocks
- added index enum in GCC clock driver
- fixed some style issues
- removed pdc patches from set

Changes from v2:
- Revised dt-bindings
- Removed qru compat strings
- Updated some clocks to use clk_branch ops instead of clk_branch2 and HALT_ENABLE

Melody Olvera (1):
  dt-bindings: clock: Add QDU1000 and QRU1000 GCC clocks

Taniya Das (1):
  clk: qcom: Add QDU1000 and QRU1000 GCC support

 .../bindings/clock/qcom,gcc-qdu1000.yaml      |   70 +
 drivers/clk/qcom/Kconfig                      |    8 +
 drivers/clk/qcom/Makefile                     |    1 +
 drivers/clk/qcom/gcc-qdu1000.c                | 2653 +++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-qdu1000.h  |  170 ++
 5 files changed, 2902 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
 create mode 100644 drivers/clk/qcom/gcc-qdu1000.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-qdu1000.h


base-commit: 147307c69ba4441ee90c1f8ce8edf5df4ea60f67

Comments

Melody Olvera Nov. 21, 2022, 8:19 p.m. UTC | #1
On 11/20/2022 5:06 AM, Krzysztof Kozlowski wrote:
> On 18/11/2022 19:18, Melody Olvera wrote:
>> Add device tree bindings for global clock controller on QDU1000 and
>> QRU1000 SoCs.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>>  .../bindings/clock/qcom,gcc-qdu1000.yaml      |  70 ++++++++
>>  include/dt-bindings/clock/qcom,gcc-qdu1000.h  | 170 ++++++++++++++++++
>>  2 files changed, 240 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
>>  create mode 100644 include/dt-bindings/clock/qcom,gcc-qdu1000.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
>> new file mode 100644
>> index 000000000000..90935a6795ee
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
>> @@ -0,0 +1,70 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,gcc-qdu1000.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
>> +
>> +allOf:
>> +  - $ref: qcom,gcc.yaml#
>> +
>> +maintainers:
>> +  - Melody Olvera <quic_molvera@quicinc.com>
>> +
>> +description: |
>> +  Qualcomm global clock control module which supports the clocks, resets and
>> +  power domains on QDU1000 and QRU1000
> Keep the same style as existing files. They were cleaned up recently.
>
>> +
>> +  See also:
>> +  - include/dt-bindings/clock/qcom,gcc-qdu1000.h
> Keep the same style, so missing '::', drop '- '.

Got it.

>
>> +
>> +properties:
>> +  compatible:
>> +    items:
>> +      - const: qcom,gcc-qdu1000
> SM8550 is coming with proper style of compatible, so let's do the same
> also here: qcom,qdu1000-gcc
> (and file name matching it)

Ok... this is fine if we're moving to a new style. sm8550 seems to have the file
name wrong in last PS.

>
>
>> +      - const: syscon
> I don't see usage of it as syscon. Which parts of GCC are needed for whom?

I think I got this from another binding. We can remove.

>
>> +
>> +  clocks:
>> +    items:
>> +      - description: Board XO source
>> +      - description: Sleep clock source
>> +      - description: PCIE 0 Pipe clock source
>> +      - description: PCIE 0 Phy Auxiliary clock source
>> +      - description: USB3 Phy wrapper pipe clock source
>> +    minItems: 2
> Same question as for SM8550 - why inputs are flexible? Either you have
> these or you do not.

Fair enough. We have these clocks so we can remove minItems.

>
>> +
>> +  '#clock-cells':
>> +    const: 1
>> +
>> +  '#reset-cells':
>> +    const: 1
>> +
>> +  '#power-domain-cells':
>> +    const: 1
> Missing ref to gcc.yaml. Drop all properties provided by gcc.yaml.

Got it.

>
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - clocks
>> +  - '#clock-cells'
>> +  - '#reset-cells'
> Drop these required by gcc.yaml.

Ack.

Thanks,
Melody
>
>
>
> Best regards,
> Krzysztof
>