| Message ID | 20221118094754.242910-18-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | tcg: Improve atomicity support | expand |
On 18/11/22 10:47, Richard Henderson wrote: > Notice when the host has additional atomic instructions. > The new variables will also be used in generated code. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/aarch64/tcg-target.h | 3 +++ > tcg/aarch64/tcg-target.c.inc | 10 ++++++++++ > 2 files changed, 13 insertions(+) > diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc > index 001a71bbc0..cf5ee6f742 100644 > --- a/tcg/aarch64/tcg-target.c.inc > +++ b/tcg/aarch64/tcg-target.c.inc > @@ -13,6 +13,8 @@ > #include "../tcg-ldst.c.inc" > #include "../tcg-pool.c.inc" > #include "qemu/bitops.h" > +#include <asm/hwcap.h> This doesn't build on Darwin: In file included from ../../tcg/tcg.c:426: tcg/aarch64/tcg-target.c.inc:16:10: fatal error: 'asm/hwcap.h' file not found #include <asm/hwcap.h> ^~~~~~~~~~~~~ In file included from ../../accel/tcg/cputlb.c:1656: ../../accel/tcg/ldst_atomicity.c.inc:269:21: warning: value size does not match register size specified by the constraint and modifier [-Wasm-operand-widths] : "=&r"(r.u), "=&r"(fail) : "Q"(*p)); ^ ../../accel/tcg/ldst_atomicity.c.inc:266:22: note: use constraint modifier "w" asm("0: ldxp %0, %R0, %2\n\t" ^~ %w0 ../../accel/tcg/ldst_atomicity.c.inc:902:9: error: invalid operand in inline asm: '0: ldxp $2, ${2:R}, $0 bic $2, $2, $4 bic ${2:R}, ${2:R}, ${4:R} orr $2, $2, $3 orr ${2:R}, ${2:R}, ${3:R} stxp ${1:w}, $2, ${2:R}, $0 cbnz ${1:w}, 0b' asm("0: ldxp %[t], %R[t], %[mem]\n\t" ^ ../../accel/tcg/ldst_atomicity.c.inc:902:9: error: invalid operand in inline asm: '0: ldxp $2, ${2:R}, $0 bic $2, $2, $4 bic ${2:R}, ${2:R}, ${4:R} orr $2, $2, $3 orr ${2:R}, ${2:R}, ${3:R} stxp ${1:w}, $2, ${2:R}, $0 cbnz ${1:w}, 0b' ../../accel/tcg/ldst_atomicity.c.inc:902:9: error: invalid operand in inline asm: '0: ldxp $2, ${2:R}, $0 bic $2, $2, $4 bic ${2:R}, ${2:R}, ${4:R} orr $2, $2, $3 orr ${2:R}, ${2:R}, ${3:R} stxp ${1:w}, $2, ${2:R}, $0 cbnz ${1:w}, 0b' ../../accel/tcg/ldst_atomicity.c.inc:902:9: error: invalid operand in inline asm: '0: ldxp $2, ${2:R}, $0 bic $2, $2, $4 bic ${2:R}, ${2:R}, ${4:R} orr $2, $2, $3 orr ${2:R}, ${2:R}, ${3:R} stxp ${1:w}, $2, ${2:R}, $0 cbnz ${1:w}, 0b' ../../accel/tcg/ldst_atomicity.c.inc:902:9: error: invalid operand in inline asm: '0: ldxp $2, ${2:R}, $0 bic $2, $2, $4 bic ${2:R}, ${2:R}, ${4:R} orr $2, $2, $3 orr ${2:R}, ${2:R}, ${3:R} stxp ${1:w}, $2, ${2:R}, $0 cbnz ${1:w}, 0b' ../../accel/tcg/ldst_atomicity.c.inc:902:9: error: invalid operand in inline asm: '0: ldxp $2, ${2:R}, $0 bic $2, $2, $4 bic ${2:R}, ${2:R}, ${4:R} orr $2, $2, $3 orr ${2:R}, ${2:R}, ${3:R} stxp ${1:w}, $2, ${2:R}, $0 cbnz ${1:w}, 0b' ../../accel/tcg/ldst_atomicity.c.inc:902:9: error: invalid operand in inline asm: '0: ldxp $2, ${2:R}, $0 bic $2, $2, $4 bic ${2:R}, ${2:R}, ${4:R} orr $2, $2, $3 orr ${2:R}, ${2:R}, ${3:R} stxp ${1:w}, $2, ${2:R}, $0 cbnz ${1:w}, 0b' ../../accel/tcg/ldst_atomicity.c.inc:902:9: error: invalid operand in inline asm: '0: ldxp $2, ${2:R}, $0 bic $2, $2, $4 bic ${2:R}, ${2:R}, ${4:R} orr $2, $2, $3 orr ${2:R}, ${2:R}, ${3:R} stxp ${1:w}, $2, ${2:R}, $0 cbnz ${1:w}, 0b' ../../accel/tcg/ldst_atomicity.c.inc:902:9: error: unknown token in expression <inline asm>:1:15: note: instantiated into assembly here 0: ldxp x13, , [x9] ^ In file included from ../../accel/tcg/cputlb.c:1656: ../../accel/tcg/ldst_atomicity.c.inc:902:9: error: invalid operand asm("0: ldxp %[t], %R[t], %[mem]\n\t" ^ <inline asm>:1:15: note: instantiated into assembly here 0: ldxp x13, , [x9] ^ In file included from ../../accel/tcg/cputlb.c:1656: ../../accel/tcg/ldst_atomicity.c.inc:903:32: error: unknown token in expression "bic %[t], %[t], %[m]\n\t" ^ <inline asm>:3:6: note: instantiated into assembly here bic , , ^ In file included from ../../accel/tcg/cputlb.c:1656: ../../accel/tcg/ldst_atomicity.c.inc:902:9: error: invalid operand in inline asm: '0: ldxp $2, ${2:R}, $0 bic $2, $2, $4 bic ${2:R}, ${2:R}, ${4:R} orr $2, $2, $3 orr ${2:R}, ${2:R}, ${3:R} stxp ${1:w}, $2, ${2:R}, $0 cbnz ${1:w}, 0b' asm("0: ldxp %[t], %R[t], %[mem]\n\t" ^ ../../accel/tcg/ldst_atomicity.c.inc:902:9: error: invalid operand in inline asm: '0: ldxp $2, ${2:R}, $0 bic $2, $2, $4 bic ${2:R}, ${2:R}, ${4:R} orr $2, $2, $3 orr ${2:R}, ${2:R}, ${3:R} stxp ${1:w}, $2, ${2:R}, $0 cbnz ${1:w}, 0b' ../../accel/tcg/ldst_atomicity.c.inc:902:9: error: invalid operand in inline asm: '0: ldxp $2, ${2:R}, $0 bic $2, $2, $4 bic ${2:R}, ${2:R}, ${4:R} orr $2, $2, $3 orr ${2:R}, ${2:R}, ${3:R} stxp ${1:w}, $2, ${2:R}, $0 cbnz ${1:w}, 0b' fatal error: too many errors emitted, stopping now [-ferror-limit=]
On 22/11/22 00:10, Philippe Mathieu-Daudé wrote: > On 18/11/22 10:47, Richard Henderson wrote: >> Notice when the host has additional atomic instructions. >> The new variables will also be used in generated code. >> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> >> --- >> tcg/aarch64/tcg-target.h | 3 +++ >> tcg/aarch64/tcg-target.c.inc | 10 ++++++++++ >> 2 files changed, 13 insertions(+) > > >> diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc >> index 001a71bbc0..cf5ee6f742 100644 >> --- a/tcg/aarch64/tcg-target.c.inc >> +++ b/tcg/aarch64/tcg-target.c.inc >> @@ -13,6 +13,8 @@ >> #include "../tcg-ldst.c.inc" >> #include "../tcg-pool.c.inc" >> #include "qemu/bitops.h" >> +#include <asm/hwcap.h> > > This doesn't build on Darwin: Project version: 7.1.91 C compiler for the host machine: clang (clang 14.0.0 "Apple clang version 14.0.0 (clang-1400.0.29.102)") C linker for the host machine: clang ld64 819.6 Host machine cpu family: aarch64 Host machine cpu: arm64 > In file included from ../../tcg/tcg.c:426: > tcg/aarch64/tcg-target.c.inc:16:10: fatal error: 'asm/hwcap.h' file not > found > #include <asm/hwcap.h> > ^~~~~~~~~~~~~ > > In file included from ../../accel/tcg/cputlb.c:1656: > ../../accel/tcg/ldst_atomicity.c.inc:269:21: warning: value size does > not match register size specified by the constraint and modifier > [-Wasm-operand-widths] > : "=&r"(r.u), "=&r"(fail) : "Q"(*p)); > ^
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 0dff5807f6..b8f734f371 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -57,6 +57,9 @@ typedef enum { #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL +extern bool have_lse; +extern bool have_lse2; + /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 #define TCG_TARGET_HAS_rem_i32 1 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 001a71bbc0..cf5ee6f742 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -13,6 +13,8 @@ #include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" #include "qemu/bitops.h" +#include <asm/hwcap.h> + /* We're going to re-use TCGType in setting of the SF bit, which controls the size of the operation performed. If we know the values match, it @@ -71,6 +73,9 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) return TCG_REG_X0 + slot; } +bool have_lse; +bool have_lse2; + #define TCG_REG_TMP TCG_REG_X30 #define TCG_VEC_TMP TCG_REG_V31 @@ -2918,6 +2923,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) static void tcg_target_init(TCGContext *s) { + unsigned long hwcap = qemu_getauxval(AT_HWCAP); + + have_lse = hwcap & HWCAP_ATOMICS; + have_lse2 = hwcap & HWCAP_USCAT; + tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu; tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu; tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
Notice when the host has additional atomic instructions. The new variables will also be used in generated code. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/aarch64/tcg-target.h | 3 +++ tcg/aarch64/tcg-target.c.inc | 10 ++++++++++ 2 files changed, 13 insertions(+)