| Message ID | 20221116214841.1116735-1-robimarko@gmail.com |
|---|---|
| State | Accepted |
| Commit | 100d9c94ccf15b02742c326cd04f422ab729153b |
| Headers | show |
| Series | [1/9] arm64: dts: qcom: ipq8074: fix Gen2 PCIe QMP PHY | expand |
On 16/11/2022 22:48, Robert Marko wrote: > IPQ8074 has one Gen2 and one Gen3 PCIe port, with Gen2 already supported. > Document Gen3 port which uses the same controller as IPQ6018. > > Signed-off-by: Robert Marko <robimarko@gmail.com> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Tue, Dec 06, 2022 at 10:51:40AM +0100, Robert Marko wrote: > On Mon, 5 Dec 2022 at 22:52, Bjorn Andersson <andersson@kernel.org> wrote: > > > > On Wed, Nov 16, 2022 at 10:48:34PM +0100, Robert Marko wrote: > > > IPQ8074 comes in 2 silicon versions: > > > * v1 with 2x Gen2 PCIe ports and QMP PHY-s > > > * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s > > > > > > v2 is the final and production version that is actually supported by the > > > kernel, however it looks like PCIe related nodes were added for the v1 SoC. > > > > > > Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support > > > by fixing the Gen3 QMP PHY node first. > > > > > > Change the compatible to the Gen3 QMP PHY, correct the register space start > > > and size, add the missing misc PCS register space. > > > > > > > Does this imply that the current node doesn't actually work? > > Hi Bjorn, > Yes, the node is for a completely different PHY generation, basically > PCIe on IPQ8074 > is completely broken, hence this patch series. > > > > > If that's the case, could we perhaps adopt Johan Hovolds' new binding > > and drop the subnode in favor of just a flat reg covering the whole > > QMP region? > > I have not seen that so far, any examples? > See Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml in v6.2-rc1. The idea is to, at least, use this for all new platforms introduced. And if the current definition doesn't actually work I suggest that we replace it with the new one. Regards, Bjorn
On Wed, Dec 28, 2022 at 12:10:17PM +0100, Robert Marko wrote: > On Tue, 27 Dec 2022 at 20:20, Bjorn Andersson <andersson@kernel.org> wrote: > > > > On Tue, Dec 06, 2022 at 10:51:40AM +0100, Robert Marko wrote: > > > On Mon, 5 Dec 2022 at 22:52, Bjorn Andersson <andersson@kernel.org> wrote: > > > > > > > > On Wed, Nov 16, 2022 at 10:48:34PM +0100, Robert Marko wrote: > > > > > IPQ8074 comes in 2 silicon versions: > > > > > * v1 with 2x Gen2 PCIe ports and QMP PHY-s > > > > > * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s > > > > > > > > > > v2 is the final and production version that is actually supported by the > > > > > kernel, however it looks like PCIe related nodes were added for the v1 SoC. > > > > > > > > > > Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support > > > > > by fixing the Gen3 QMP PHY node first. > > > > > > > > > > Change the compatible to the Gen3 QMP PHY, correct the register space start > > > > > and size, add the missing misc PCS register space. > > > > > > > > > > > > > Does this imply that the current node doesn't actually work? > > > > > > Hi Bjorn, > > > Yes, the node is for a completely different PHY generation, basically > > > PCIe on IPQ8074 > > > is completely broken, hence this patch series. > > > > > > > > > > > If that's the case, could we perhaps adopt Johan Hovolds' new binding > > > > and drop the subnode in favor of just a flat reg covering the whole > > > > QMP region? > > > > > > I have not seen that so far, any examples? > > > > > > > See > > Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml in > > v6.2-rc1. > > > > The idea is to, at least, use this for all new platforms introduced. > > > > And if the current definition doesn't actually work I suggest that we > > replace it with the new one. > > I understand the intention, but these bindings dont match the QMP generation > found in IPQ8074 at all, and Gen3 has already been documented in bindings. > > This would require updating the driver to carry the offsets and rework > of bindings to > not require power domains, etc for IPQ8074 as I have not found any > code downstream > to indicate it has GSDC-s for PCIe though I dont have any docs at all > for the SoC. > I was only thinking of the structural difference, not the power-domains etc. But yes you're right that it means updating the driver and the binding. The end result would be much nicer though... Regards, Bjorn
On Wed, Nov 16, 2022 at 10:48:38PM +0100, Robert Marko wrote: > IPQ8074 has one Gen2 and one Gen3 PCIe port, with Gen2 already supported. > Document Gen3 port which uses the same controller as IPQ6018. > > Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Thanks, Mani > --- > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index 1e94c210429a..59f4c9990f85 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -24,6 +24,7 @@ properties: > - qcom,pcie-ipq8064 > - qcom,pcie-ipq8064-v2 > - qcom,pcie-ipq8074 > + - qcom,pcie-ipq8074-gen3 > - qcom,pcie-msm8996 > - qcom,pcie-qcs404 > - qcom,pcie-sa8540p > @@ -151,6 +152,7 @@ allOf: > contains: > enum: > - qcom,pcie-ipq6018 > + - qcom,pcie-ipq8074-gen3 > then: > properties: > reg: > @@ -371,6 +373,7 @@ allOf: > contains: > enum: > - qcom,pcie-ipq6018 > + - qcom,pcie-ipq8074-gen3 > then: > properties: > clocks: > @@ -662,6 +665,7 @@ allOf: > - qcom,pcie-ipq8064 > - qcom,pcie-ipq8064v2 > - qcom,pcie-ipq8074 > + - qcom,pcie-ipq8074-gen3 > - qcom,pcie-qcs404 > then: > required: > @@ -744,6 +748,7 @@ allOf: > - qcom,pcie-ipq8064 > - qcom,pcie-ipq8064-v2 > - qcom,pcie-ipq8074 > + - qcom,pcie-ipq8074-gen3 > - qcom,pcie-qcs404 > - qcom,pcie-sa8540p > then: > -- > 2.38.1 >
On Wed, Nov 16, 2022 at 10:48:37PM +0100, Robert Marko wrote: > Sort the compatibles list alphabetically for maintenance. > > Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Thanks, Mani > --- > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index 2f851c804bb0..1e94c210429a 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -17,13 +17,14 @@ description: | > properties: > compatible: > enum: > - - qcom,pcie-ipq8064 > - - qcom,pcie-ipq8064-v2 > - qcom,pcie-apq8064 > - qcom,pcie-apq8084 > - - qcom,pcie-msm8996 > - qcom,pcie-ipq4019 > + - qcom,pcie-ipq6018 > + - qcom,pcie-ipq8064 > + - qcom,pcie-ipq8064-v2 > - qcom,pcie-ipq8074 > + - qcom,pcie-msm8996 > - qcom,pcie-qcs404 > - qcom,pcie-sa8540p > - qcom,pcie-sc7280 > @@ -34,7 +35,6 @@ properties: > - qcom,pcie-sm8250 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > - - qcom,pcie-ipq6018 > > reg: > minItems: 4 > -- > 2.38.1 >
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 4b4cd3eaf6c8..6649a758d8df 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -277,9 +277,9 @@ pcie_qmp1: phy@8e000 { status = "disabled"; pcie_phy1: phy@8e200 { - reg = <0x8e200 0x16c>, + reg = <0x8e200 0x130>, <0x8e400 0x200>, - <0x8e800 0x4f4>; + <0x8e800 0x1f8>; #phy-cells = <0>; #clock-cells = <0>; clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
Serdes register space sizes are incorrect, update them to match the actual sizes from downstream QCA 5.4 kernel. Fixes: 942bcd33ed45 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes") Signed-off-by: Robert Marko <robimarko@gmail.com> --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)