diff mbox series

tcg/riscv: Fix range matched by TCG_CT_CONST_M12

Message ID 20221022095821.2441874-1-richard.henderson@linaro.org
State Accepted
Commit 627227636127c44df0e01ab8fd9fae3f731fa8b0
Headers show
Series tcg/riscv: Fix range matched by TCG_CT_CONST_M12 | expand

Commit Message

Richard Henderson Oct. 22, 2022, 9:58 a.m. UTC
We were matching a signed 13-bit range, not a 12-bit range.
Expand the commentary within the function and be explicit
about all of the ranges.

Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/riscv/tcg-target.c.inc | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

Comments

LIU Zhiwei Oct. 23, 2022, noon UTC | #1
On 2022/10/22 17:58, Richard Henderson wrote:
> We were matching a signed 13-bit range, not a 12-bit range.
> Expand the commentary within the function and be explicit
> about all of the ranges.
>
> Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
>   tcg/riscv/tcg-target.c.inc | 19 ++++++++++++++++---
>   1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 1cdaf7b57b..2a84c57bec 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -154,13 +154,26 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
>       if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
>           return 1;
>       }
> -    if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
> +    /*
> +     * Sign extended from 12 bits: [-0x800, 0x7ff].
> +     * Used for most arithmetic, as this is the isa field.
> +     */
> +    if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) {
>           return 1;
>       }
> -    if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
> +    /*
> +     * Sign extended from 12 bits, negated: [-0x7ff, 0x800].
> +     * Used for subtraction, where a constant must be handled by ADDI.
> +     */
> +    if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) {
>           return 1;
>       }
> -    if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
> +    /*
> +     * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff].
> +     * Used by addsub2, which may need the negative operation,
> +     * and requires the modified constant to be representable.
> +     */
> +    if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) {
>           return 1;
>       }
>       return 0;
Alistair Francis Oct. 25, 2022, 12:21 a.m. UTC | #2
On Sat, Oct 22, 2022 at 8:19 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We were matching a signed 13-bit range, not a 12-bit range.
> Expand the commentary within the function and be explicit
> about all of the ranges.
>
> Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  tcg/riscv/tcg-target.c.inc | 19 ++++++++++++++++---
>  1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 1cdaf7b57b..2a84c57bec 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -154,13 +154,26 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
>      if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
>          return 1;
>      }
> -    if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
> +    /*
> +     * Sign extended from 12 bits: [-0x800, 0x7ff].
> +     * Used for most arithmetic, as this is the isa field.
> +     */
> +    if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) {
>          return 1;
>      }
> -    if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
> +    /*
> +     * Sign extended from 12 bits, negated: [-0x7ff, 0x800].
> +     * Used for subtraction, where a constant must be handled by ADDI.
> +     */
> +    if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) {
>          return 1;
>      }
> -    if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
> +    /*
> +     * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff].
> +     * Used by addsub2, which may need the negative operation,
> +     * and requires the modified constant to be representable.
> +     */
> +    if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) {
>          return 1;
>      }
>      return 0;
> --
> 2.34.1
>
>
Alistair Francis Oct. 25, 2022, 1:30 a.m. UTC | #3
On Sat, Oct 22, 2022 at 8:19 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We were matching a signed 13-bit range, not a 12-bit range.
> Expand the commentary within the function and be explicit
> about all of the ranges.
>
> Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  tcg/riscv/tcg-target.c.inc | 19 ++++++++++++++++---
>  1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 1cdaf7b57b..2a84c57bec 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -154,13 +154,26 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
>      if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
>          return 1;
>      }
> -    if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
> +    /*
> +     * Sign extended from 12 bits: [-0x800, 0x7ff].
> +     * Used for most arithmetic, as this is the isa field.
> +     */
> +    if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) {
>          return 1;
>      }
> -    if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
> +    /*
> +     * Sign extended from 12 bits, negated: [-0x7ff, 0x800].
> +     * Used for subtraction, where a constant must be handled by ADDI.
> +     */
> +    if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) {
>          return 1;
>      }
> -    if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
> +    /*
> +     * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff].
> +     * Used by addsub2, which may need the negative operation,
> +     * and requires the modified constant to be representable.
> +     */
> +    if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) {
>          return 1;
>      }
>      return 0;
> --
> 2.34.1
>
>
diff mbox series

Patch

diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 1cdaf7b57b..2a84c57bec 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -154,13 +154,26 @@  static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
     if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
         return 1;
     }
-    if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
+    /*
+     * Sign extended from 12 bits: [-0x800, 0x7ff].
+     * Used for most arithmetic, as this is the isa field.
+     */
+    if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) {
         return 1;
     }
-    if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
+    /*
+     * Sign extended from 12 bits, negated: [-0x7ff, 0x800].
+     * Used for subtraction, where a constant must be handled by ADDI.
+     */
+    if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) {
         return 1;
     }
-    if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
+    /*
+     * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff].
+     * Used by addsub2, which may need the negative operation,
+     * and requires the modified constant to be representable.
+     */
+    if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) {
         return 1;
     }
     return 0;