Message ID | 20221014221011.7360-1-quic_molvera@quicinc.com |
---|---|
Headers | show |
Series | clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs | expand |
On 10/14/2022 3:10 PM, Melody Olvera wrote: > This series adds the GCC, RPMh, and PDC clock support required for the > QDU1000 and QRU1000 SoCs along with the devicetree bindings for them. > > The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit > 1000 are new SoCs meant for enabling Open RAN solutions. See more at > https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf > > This patchset is based on the YAML conversion patch [1] submitted already. > > [1] https://lore.kernel.org/r/20220103074348.6039-1-luca.weiss@fairphone.com Changes from V1: - fixed alphabetic sorting - moved clk-branch changes to a separate commit - revised bindings > Imran Shaik (1): > clk: qcom: branch: Add BRANCH_HALT_INVERT flag support for branch > clocks > > Melody Olvera (4): > dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings > dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000 > clk: qcom: Add support for QDU1000 and QRU1000 RPMh clocks > dt-bindings: qcom,pdc: Introduce pdc bindings for QDU1000 and QRU1000 > > Taniya Das (1): > clk: qcom: Add QDU1000 and QRU1000 GCC support > > .../bindings/clock/qcom,gcc-qdu1000.yaml | 70 + > .../bindings/clock/qcom,rpmhcc.yaml | 2 + > .../interrupt-controller/qcom,pdc.yaml | 2 + > drivers/clk/qcom/Kconfig | 8 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/clk-branch.c | 5 + > drivers/clk/qcom/clk-branch.h | 2 + > drivers/clk/qcom/clk-rpmh.c | 14 + > drivers/clk/qcom/gcc-qdu1000.c | 2644 +++++++++++++++++ > include/dt-bindings/clock/qcom,gcc-qdu1000.h | 170 ++ > 10 files changed, 2918 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml > create mode 100644 drivers/clk/qcom/gcc-qdu1000.c > create mode 100644 include/dt-bindings/clock/qcom,gcc-qdu1000.h > > > base-commit: dca0a0385a4963145593ba417e1417af88a7c18d
On 14/10/2022 18:10, Melody Olvera wrote: > Add device tree bindings for global clock controller on QDU1000 and > QRU1000 SoCs. > > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> > --- > .../bindings/clock/qcom,gcc-qdu1000.yaml | 70 ++++++++ > include/dt-bindings/clock/qcom,gcc-qdu1000.h | 170 ++++++++++++++++++ > 2 files changed, 240 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml > create mode 100644 include/dt-bindings/clock/qcom,gcc-qdu1000.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml > new file mode 100644 > index 000000000000..b0746669e2ad > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,gcc-qdu1000.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000 > + > +maintainers: > + - Melody Olvera <quic_molvera@quicinc.com> > + > +description: | > + Qualcomm global clock control module which supports the clocks, resets and > + power domains on QDU1000 and QRU1000 > + > + See also: > + - include/dt-bindings/clock/qcom,gcc-qdu1000.h > + > +properties: > + compatible: > + enum: > + - qcom,gcc-qdu1000 > + - qcom,gcc-qru1000 > + > + clocks: > + items: > + - description: Board XO source > + - description: Sleep clock source > + - description: PCIE 0 Pipe clock source > + - description: PCIE 0 Phy Auxiliary clock source > + - description: USB3 Phy wrapper pipe clock source > + minItems: 2 > + > + clock-names: > + items: > + - const: bi_tcxo > + - const: sleep_clk > + - const: pcie_0_pipe_clk This does not match your clocks, please test your bindings. I thought you understood my comment when you confirmed misunderstanding... Best regards, Krzysztof
On 14/10/2022 19:53, Melody Olvera wrote: > > > On 10/14/2022 3:10 PM, Melody Olvera wrote: >> This series adds the GCC, RPMh, and PDC clock support required for the >> QDU1000 and QRU1000 SoCs along with the devicetree bindings for them. >> >> The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit >> 1000 are new SoCs meant for enabling Open RAN solutions. See more at >> https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf >> >> This patchset is based on the YAML conversion patch [1] submitted already. >> >> [1] https://lore.kernel.org/r/20220103074348.6039-1-luca.weiss@fairphone.com > Changes from V1: > - fixed alphabetic sorting > - moved clk-branch changes to a separate commit > - revised binding This must be in the cover letter, not as a reply. Best regards, Krzysztof
On 14/10/2022 18:10, Melody Olvera wrote: > Add compatible fields for QDU1000 and QRU1000 pdcs. > > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> > --- > .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof