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[0/8] MIPS: ingenic: Add support for the JZ4755 SoC

Message ID 20221009181338.2896660-1-lis8215@gmail.com
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Series MIPS: ingenic: Add support for the JZ4755 SoC | expand

Message

Siarhei Volkau Oct. 9, 2022, 6:13 p.m. UTC
Add preliminary support for boards based on the JZ4755 SoC from
Ingenic.

It is a low-power SoC with a MIPS32r1 core running at ~432 MHz,
and has no FPU.

The JZ4755 SoC is supposed to be newer than the JZ4725B SoC, but its
internals are very close to each other. Also the Ingenic's kernel
source tree calls JZ4755 as JZ4750D and JZ4725B as JZ4750L, this might
mean that JZ4725B is a pin to pin compatible replacement for older
JZ4725 (both are LQFP128) but belongs to newer generation JZ475x. Who
knows?

I guess Ingenic released their SoCs in the following order:
 JZ4720  (MXU ?)
 JZ4725  (MXU ?)
 JZ4730  (MXU ?)
 JZ4740  (MXU1 r1)
 JZ4750  (MXU1 r2)
 JZ4755  (MXU1 r2)
 JZ4725b (MXU1 r2)
 JZ4760  ...

So JZ4755 DT is reusing many JZ4725B drivers because their support
in mainline kernel appears earlier.

Siarhei Volkau (8):
  dt-bindings: ingenic: Add support for the JZ4755 SoC
  MIPS: ingenic: add new machine type MACH_JZ4755
  dt-bindings: clock: Add Ingenic JZ4755 CGU header
  clk: Add Ingenic JZ4755 CGU driver
  pinctrl: ingenic: JZ4755 minor bug fixes
  dmaengine: JZ4780: Add support for the JZ4755.
  serial: 8250/ingenic: Add support for the JZ4750/JZ4755 SoCs
  MIPS: ingenic: Add support for the JZ4755 SoC

 .../bindings/clock/ingenic,cgu.yaml           |   2 +
 .../devicetree/bindings/dma/ingenic,dma.yaml  |   1 +
 .../bindings/serial/ingenic,uart.yaml         |   4 +
 arch/mips/boot/dts/ingenic/jz4755.dtsi        | 439 ++++++++++++++++++
 arch/mips/ingenic/Kconfig                     |   5 +
 drivers/clk/ingenic/Kconfig                   |  10 +
 drivers/clk/ingenic/Makefile                  |   1 +
 drivers/clk/ingenic/jz4755-cgu.c              | 350 ++++++++++++++
 drivers/dma/dma-jz4780.c                      |   8 +
 drivers/pinctrl/pinctrl-ingenic.c             |   4 +-
 drivers/tty/serial/8250/8250_ingenic.c        |  39 +-
 .../dt-bindings/clock/ingenic,jz4755-cgu.h    |  49 ++
 12 files changed, 905 insertions(+), 7 deletions(-)
 create mode 100644 arch/mips/boot/dts/ingenic/jz4755.dtsi
 create mode 100644 drivers/clk/ingenic/jz4755-cgu.c
 create mode 100644 include/dt-bindings/clock/ingenic,jz4755-cgu.h

Comments

Rob Herring (Arm) Oct. 10, 2022, 1:05 p.m. UTC | #1
On Sun, Oct 09, 2022 at 09:13:32PM +0300, Siarhei Volkau wrote:
> This will be used from the devicetree bindings to specify the clocks
> that should be obtained from the jz4755-cgu driver.
> 
> Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
> ---
>  .../dt-bindings/clock/ingenic,jz4755-cgu.h    | 49 +++++++++++++++++++
>  1 file changed, 49 insertions(+)
>  create mode 100644 include/dt-bindings/clock/ingenic,jz4755-cgu.h
> 
> diff --git a/include/dt-bindings/clock/ingenic,jz4755-cgu.h b/include/dt-bindings/clock/ingenic,jz4755-cgu.h
> new file mode 100644
> index 000000000..32307f68c
> --- /dev/null
> +++ b/include/dt-bindings/clock/ingenic,jz4755-cgu.h
> @@ -0,0 +1,49 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

Dual license please.

> +/*
> + * This header provides clock numbers for the ingenic,jz4755-cgu DT binding.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_JZ4755_CGU_H__
> +#define __DT_BINDINGS_CLOCK_JZ4755_CGU_H__
> +
> +#define JZ4755_CLK_EXT		0
> +#define JZ4755_CLK_OSC32K	1
> +#define JZ4755_CLK_PLL		2
> +#define JZ4755_CLK_PLL_HALF	3
> +#define JZ4755_CLK_EXT_HALF	4
> +#define JZ4755_CLK_CCLK		5
> +#define JZ4755_CLK_H0CLK	6
> +#define JZ4755_CLK_PCLK		7
> +#define JZ4755_CLK_MCLK		8
> +#define JZ4755_CLK_H1CLK	9
> +#define JZ4755_CLK_UDC		10
> +#define JZ4755_CLK_LCD		11
> +#define JZ4755_CLK_UART0	12
> +#define JZ4755_CLK_UART1	13
> +#define JZ4755_CLK_UART2	14
> +#define JZ4755_CLK_DMA		15
> +#define JZ4755_CLK_MMC		16
> +#define JZ4755_CLK_MMC0		17
> +#define JZ4755_CLK_MMC1		18
> +#define JZ4755_CLK_EXT512	19
> +#define JZ4755_CLK_RTC		20
> +#define JZ4755_CLK_UDC_PHY	21
> +#define JZ4755_CLK_I2S		22
> +#define JZ4755_CLK_SPI		23
> +#define JZ4755_CLK_AIC		24
> +#define JZ4755_CLK_ADC		25
> +#define JZ4755_CLK_TCU		26
> +#define JZ4755_CLK_BCH		27
> +#define JZ4755_CLK_I2C		28
> +#define JZ4755_CLK_TVE		29
> +#define JZ4755_CLK_CIM		30
> +#define JZ4755_CLK_AUX_CPU	31
> +#define JZ4755_CLK_AHB1		32
> +#define JZ4755_CLK_IDCT		33
> +#define JZ4755_CLK_DB		34
> +#define JZ4755_CLK_ME		35
> +#define JZ4755_CLK_MC		36
> +#define JZ4755_CLK_TSSI		37
> +#define JZ4755_CLK_IPU		38
> +
> +#endif /* __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ */
> -- 
> 2.36.1
> 
>
Krzysztof Kozlowski Oct. 10, 2022, 2:53 p.m. UTC | #2
On 09/10/2022 14:13, Siarhei Volkau wrote:
> JZ4755 is a low-power SoC similar to JZ4725B which is already here.
> 
> The patch adds compatibles for parts which aren't implemented yet and
> they are subject of this patch serie.
> 
> Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
> ---
>  Documentation/devicetree/bindings/clock/ingenic,cgu.yaml   | 2 ++
>  Documentation/devicetree/bindings/dma/ingenic,dma.yaml     | 1 +
>  Documentation/devicetree/bindings/serial/ingenic,uart.yaml | 4 ++++

How do you plan to merge it? Usually these go via subsystem trees...


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof
Siarhei Volkau Oct. 10, 2022, 8:18 p.m. UTC | #3
пн, 10 окт. 2022 г. в 17:55, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org>:

> How do you plan to merge it? Usually these go via subsystem trees...

It's a new case for me, could you explain the problem a bit more?
What things should I bother with in the next patchset version?
Thanks in advance.
Krzysztof Kozlowski Oct. 11, 2022, 12:08 p.m. UTC | #4
On 10/10/2022 16:18, Siarhei Volkau wrote:
> пн, 10 окт. 2022 г. в 17:55, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org>:
> 
>> How do you plan to merge it? Usually these go via subsystem trees...
> 
> It's a new case for me, could you explain the problem a bit more?
> What things should I bother with in the next patchset version?
> Thanks in advance.

Each binding goes via subsystem maintainer, not via DT bindings tree, so
keeping all in one patch messes with that.

Best regards,
Krzysztof
Siarhei Volkau Oct. 11, 2022, 6:38 p.m. UTC | #5
пн, 10 окт. 2022 г. в 23:20, Greg Kroah-Hartman <gregkh@linuxfoundation.org>:
> What does "clkdiv" mean here?

That means a clock divisor between the input oscillator and UART
peripheral clock source. Most Ingenic SoCs don't have that divisor,
so 1 is always in effect for them.
However, the JZ4750 and JZ4755 have switchable /2 clock divisor.

> If you only have 1 or 2 as an option

Yes, it is.

> just have 2 functions instead please.

Got it, will do that.

Thank you.