diff mbox series

[2/2] dt-bindings: pinctrl: qcom,sdm845: convert to dtschema

Message ID 20220930200529.331223-3-krzysztof.kozlowski@linaro.org
State Accepted
Commit dba79c34605d60cb02c2951c701ea0bc16937153
Headers show
Series pinctrl/arm64: qcom: convert sdm845 bindings to DT schema | expand

Commit Message

Krzysztof Kozlowski Sept. 30, 2022, 8:05 p.m. UTC 
Convert Qualcomm SDM845 pin controller bindings to DT schema.  Keep
the parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../bindings/pinctrl/qcom,sdm845-pinctrl.txt  | 176 ------------------
 .../bindings/pinctrl/qcom,sdm845-pinctrl.yaml | 158 ++++++++++++++++
 2 files changed, 158 insertions(+), 176 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml

Comments

Rob Herring (Arm) Sept. 30, 2022, 10:05 p.m. UTC | #1 
On Fri, 30 Sep 2022 22:05:29 +0200, Krzysztof Kozlowski wrote:
> Convert Qualcomm SDM845 pin controller bindings to DT schema.  Keep
> the parsing of pin configuration subnodes consistent with other Qualcomm
> schemas (children named with '-state' suffix, their children with
> '-pins').
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
>  .../bindings/pinctrl/qcom,sdm845-pinctrl.txt  | 176 ------------------
>  .../bindings/pinctrl/qcom,sdm845-pinctrl.yaml | 158 ++++++++++++++++
>  2 files changed, 158 insertions(+), 176 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml
> 

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/


pinctrl@3400000: 'ap-edp-bklten', 'ap-suspend-l-hog', 'ap_suspend_l_assert', 'ap_suspend_l_deassert', 'bios-flash-wp-r-l', 'cci0-default', 'cci0-sleep', 'cci1-default', 'cci1-sleep', 'ec-ap-int-l', 'edp-brij-en', 'edp-brij-irq', 'en-pp3300-dx-edp', 'h1-ap-int-odl', 'pen-eject-odl', 'pen-irq-l', 'pen-pdct-l', 'pen-rst-l', 'qspi-clk', 'qspi-cs0', 'qspi-cs1', 'qspi-data01', 'qspi-data12', 'quat_mi2s_active', 'quat_mi2s_sd0_active', 'quat_mi2s_sd0_sleep', 'quat_mi2s_sd1_active', 'quat_mi2s_sd1_sleep', 'quat_mi2s_sd2_active', 'quat_mi2s_sd2_sleep', 'quat_mi2s_sd3_active', 'quat_mi2s_sd3_sleep', 'quat_mi2s_sleep', 'qup-i2c0-default', 'qup-i2c1-default', 'qup-i2c10-default', 'qup-i2c11-default', 'qup-i2c12-default', 'qup-i2c13-default', 'qup-i2c14-default', 'qup-i2c15-default', 'qup-i2c2-default', 'qup-i2c3-default', 'qup-i2c4-default', 'qup-i2c5-default', 'qup-i2c6-default', 'qup-i2c7-default', 'qup-i2c8-default', 'qup-i2c9-default', 'qup-spi0-default', 'qup-spi1-default', 'qup-spi10-defau
 lt', 'qup-spi11-default', 'qup-spi12-default', 'qup-spi13-default', 'qup-spi14-default', 'qup-spi15-default', 'qup-spi2-default', 'qup-spi3-default', 'qup-spi4-default', 'qup-spi5-default', 'qup-spi6-default', 'qup-spi7-default', 'qup-spi8-default', 'qup-spi9-default', 'qup-uart0-default', 'qup-uart1-default', 'qup-uart10-default', 'qup-uart11-default', 'qup-uart12-default', 'qup-uart13-default', 'qup-uart14-default', 'qup-uart15-default', 'qup-uart2-default', 'qup-uart3-default', 'qup-uart4-default', 'qup-uart5-default', 'qup-uart6-default', 'qup-uart7-default', 'qup-uart8-default', 'qup-uart9-default', 'sd-cd-odl', 'sdc2-clk', 'sdc2-cmd', 'sdc2-data', 'ts-int-l', 'ts-reset-l' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
	arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dtb
	arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dtb
	arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dtb

pinctrl@3400000: 'cam0_default', 'cam3_default', 'cci0-default', 'cci0-sleep', 'cci1-default', 'cci1-sleep', 'dsi-sw-sel', 'lt9611-irq', 'pcie0-default', 'pcie0-pwren', 'pcie1-default', 'qspi-clk', 'qspi-cs0', 'qspi-cs1', 'qspi-data01', 'qspi-data12', 'quat_mi2s_active', 'quat_mi2s_sd0_active', 'quat_mi2s_sd0_sleep', 'quat_mi2s_sd1_active', 'quat_mi2s_sd1_sleep', 'quat_mi2s_sd2_active', 'quat_mi2s_sd2_sleep', 'quat_mi2s_sd3_active', 'quat_mi2s_sd3_sleep', 'quat_mi2s_sleep', 'qup-i2c0-default', 'qup-i2c1-default', 'qup-i2c10-default', 'qup-i2c11-default', 'qup-i2c12-default', 'qup-i2c13-default', 'qup-i2c14-default', 'qup-i2c15-default', 'qup-i2c2-default', 'qup-i2c3-default', 'qup-i2c4-default', 'qup-i2c5-default', 'qup-i2c6-default', 'qup-i2c7-default', 'qup-i2c8-default', 'qup-i2c9-default', 'qup-spi0-default', 'qup-spi1-default', 'qup-spi10-default', 'qup-spi11-default', 'qup-spi12-default', 'qup-spi13-default', 'qup-spi14-default', 'qup-spi15-default', 'qup-spi2-default', 'qup-sp
 i3-default', 'qup-spi4-default', 'qup-spi5-default', 'qup-spi6-default', 'qup-spi7-default', 'qup-spi8-default', 'qup-spi9-default', 'qup-uart0-default', 'qup-uart1-default', 'qup-uart10-default', 'qup-uart11-default', 'qup-uart12-default', 'qup-uart13-default', 'qup-uart14-default', 'qup-uart15-default', 'qup-uart2-default', 'qup-uart3-default', 'qup-uart4-default', 'qup-uart5-default', 'qup-uart6-default', 'qup-uart7-default', 'qup-uart8-default', 'qup-uart9-default', 'sd-card-det-n', 'sdc2-default', 'wcd_intr_default' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
	arch/arm64/boot/dts/qcom/sdm845-db845c.dtb

pinctrl@3400000: 'cci0-default', 'cci0-sleep', 'cci1-default', 'cci1-sleep', 'i2c11-hid-active', 'i2c2-hid-active', 'i2c5-hid-active', 'lid-pin', 'mode-pin', 'qspi-clk', 'qspi-cs0', 'qspi-cs1', 'qspi-data01', 'qspi-data12', 'quat_mi2s_active', 'quat_mi2s_sd0_active', 'quat_mi2s_sd0_sleep', 'quat_mi2s_sd1_active', 'quat_mi2s_sd1_sleep', 'quat_mi2s_sd2_active', 'quat_mi2s_sd2_sleep', 'quat_mi2s_sd3_active', 'quat_mi2s_sd3_sleep', 'quat_mi2s_sleep', 'qup-i2c0-default', 'qup-i2c1-default', 'qup-i2c10-default', 'qup-i2c11-default', 'qup-i2c12-default', 'qup-i2c13-default', 'qup-i2c14-default', 'qup-i2c15-default', 'qup-i2c2-default', 'qup-i2c3-default', 'qup-i2c4-default', 'qup-i2c5-default', 'qup-i2c6-default', 'qup-i2c7-default', 'qup-i2c8-default', 'qup-i2c9-default', 'qup-spi0-default', 'qup-spi1-default', 'qup-spi10-default', 'qup-spi11-default', 'qup-spi12-default', 'qup-spi13-default', 'qup-spi14-default', 'qup-spi15-default', 'qup-spi2-default', 'qup-spi3-default', 'qup-spi4-defau
 lt', 'qup-spi5-default', 'qup-spi6-default', 'qup-spi7-default', 'qup-spi8-default', 'qup-spi9-default', 'qup-uart0-default', 'qup-uart1-default', 'qup-uart10-default', 'qup-uart11-default', 'qup-uart12-default', 'qup-uart13-default', 'qup-uart14-default', 'qup-uart15-default', 'qup-uart2-default', 'qup-uart3-default', 'qup-uart4-default', 'qup-uart5-default', 'qup-uart6-default', 'qup-uart7-default', 'qup-uart8-default', 'qup-uart9-default', 'sn65dsi86-enable', 'wcd_intr_default' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
	arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dtb

pinctrl@3400000: 'cci0-default', 'cci0-sleep', 'cci1-default', 'cci1-sleep', 'panel-esd', 'panel-reset', 'panel-te', 'qspi-clk', 'qspi-cs0', 'qspi-cs1', 'qspi-data01', 'qspi-data12', 'quat_mi2s_active', 'quat_mi2s_sd0_active', 'quat_mi2s_sd0_sleep', 'quat_mi2s_sd1_active', 'quat_mi2s_sd1_sleep', 'quat_mi2s_sd2_active', 'quat_mi2s_sd2_sleep', 'quat_mi2s_sd3_active', 'quat_mi2s_sd3_sleep', 'quat_mi2s_sleep', 'qup-i2c0-default', 'qup-i2c1-default', 'qup-i2c10-default', 'qup-i2c11-default', 'qup-i2c12-default', 'qup-i2c13-default', 'qup-i2c14-default', 'qup-i2c15-default', 'qup-i2c2-default', 'qup-i2c3-default', 'qup-i2c4-default', 'qup-i2c5-default', 'qup-i2c6-default', 'qup-i2c7-default', 'qup-i2c8-default', 'qup-i2c9-default', 'qup-spi0-default', 'qup-spi1-default', 'qup-spi10-default', 'qup-spi11-default', 'qup-spi12-default', 'qup-spi13-default', 'qup-spi14-default', 'qup-spi15-default', 'qup-spi2-default', 'qup-spi3-default', 'qup-spi4-default', 'qup-spi5-default', 'qup-spi6-defaul
 t', 'qup-spi7-default', 'qup-spi8-default', 'qup-spi9-default', 'qup-uart0-default', 'qup-uart1-default', 'qup-uart10-default', 'qup-uart11-default', 'qup-uart12-default', 'qup-uart13-default', 'qup-uart14-default', 'qup-uart15-default', 'qup-uart2-default', 'qup-uart3-default', 'qup-uart4-default', 'qup-uart5-default', 'qup-uart6-default', 'qup-uart7-default', 'qup-uart8-default', 'qup-uart9-default', 'tri_state_key_default', 'ts-int' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
	arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dtb
	arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dtb

pinctrl@3400000: 'cci0-default', 'cci0-sleep', 'cci1-default', 'cci1-sleep', 'pen-irq-l', 'pen-pdct-l', 'pen-rst-l', 'qspi-clk', 'qspi-cs0', 'qspi-cs1', 'qspi-data01', 'qspi-data12', 'quat_mi2s_active', 'quat_mi2s_sd0_active', 'quat_mi2s_sd0_sleep', 'quat_mi2s_sd1_active', 'quat_mi2s_sd1_sleep', 'quat_mi2s_sd2_active', 'quat_mi2s_sd2_sleep', 'quat_mi2s_sd3_active', 'quat_mi2s_sd3_sleep', 'quat_mi2s_sleep', 'qup-i2c0-default', 'qup-i2c1-default', 'qup-i2c10-default', 'qup-i2c11-default', 'qup-i2c12-default', 'qup-i2c13-default', 'qup-i2c14-default', 'qup-i2c15-default', 'qup-i2c2-default', 'qup-i2c3-default', 'qup-i2c4-default', 'qup-i2c5-default', 'qup-i2c6-default', 'qup-i2c7-default', 'qup-i2c8-default', 'qup-i2c9-default', 'qup-spi0-default', 'qup-spi1-default', 'qup-spi10-default', 'qup-spi11-default', 'qup-spi12-default', 'qup-spi13-default', 'qup-spi14-default', 'qup-spi15-default', 'qup-spi2-default', 'qup-spi3-default', 'qup-spi4-default', 'qup-spi5-default', 'qup-spi6-defaul
 t', 'qup-spi7-default', 'qup-spi8-default', 'qup-spi9-default', 'qup-uart0-default', 'qup-uart1-default', 'qup-uart10-default', 'qup-uart11-default', 'qup-uart12-default', 'qup-uart13-default', 'qup-uart14-default', 'qup-uart15-default', 'qup-uart2-default', 'qup-uart3-default', 'qup-uart4-default', 'qup-uart5-default', 'qup-uart6-default', 'qup-uart7-default', 'qup-uart8-default', 'qup-uart9-default', 'wcd_intr_default' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
	arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dtb

pinctrl@3400000: 'cci0-default', 'cci0-sleep', 'cci1-default', 'cci1-sleep', 'qspi-clk', 'qspi-cs0', 'qspi-cs1', 'qspi-data01', 'qspi-data12', 'quat_mi2s_active', 'quat_mi2s_sd0_active', 'quat_mi2s_sd0_sleep', 'quat_mi2s_sd1_active', 'quat_mi2s_sd1_sleep', 'quat_mi2s_sd2_active', 'quat_mi2s_sd2_sleep', 'quat_mi2s_sd3_active', 'quat_mi2s_sd3_sleep', 'quat_mi2s_sleep', 'qup-i2c0-default', 'qup-i2c1-default', 'qup-i2c10-default', 'qup-i2c11-default', 'qup-i2c12-default', 'qup-i2c13-default', 'qup-i2c14-default', 'qup-i2c15-default', 'qup-i2c2-default', 'qup-i2c3-default', 'qup-i2c4-default', 'qup-i2c5-default', 'qup-i2c6-default', 'qup-i2c7-default', 'qup-i2c8-default', 'qup-i2c9-default', 'qup-spi0-default', 'qup-spi1-default', 'qup-spi10-default', 'qup-spi11-default', 'qup-spi12-default', 'qup-spi13-default', 'qup-spi14-default', 'qup-spi15-default', 'qup-spi2-default', 'qup-spi3-default', 'qup-spi4-default', 'qup-spi5-default', 'qup-spi6-default', 'qup-spi7-default', 'qup-spi8-defaul
 t', 'qup-spi9-default', 'qup-uart0-default', 'qup-uart1-default', 'qup-uart10-default', 'qup-uart11-default', 'qup-uart12-default', 'qup-uart13-default', 'qup-uart14-default', 'qup-uart15-default', 'qup-uart2-default', 'qup-uart3-default', 'qup-uart4-default', 'qup-uart5-default', 'qup-uart6-default', 'qup-uart7-default', 'qup-uart8-default', 'qup-uart9-default' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
	arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dtb
	arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dtb
	arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dtb

pinctrl@3400000: 'cci0-default', 'cci0-sleep', 'cci1-default', 'cci1-sleep', 'qspi-clk', 'qspi-cs0', 'qspi-cs1', 'qspi-data01', 'qspi-data12', 'quat_mi2s_active', 'quat_mi2s_sd0_active', 'quat_mi2s_sd0_sleep', 'quat_mi2s_sd1_active', 'quat_mi2s_sd1_sleep', 'quat_mi2s_sd2_active', 'quat_mi2s_sd2_sleep', 'quat_mi2s_sd3_active', 'quat_mi2s_sd3_sleep', 'quat_mi2s_sleep', 'qup-i2c0-default', 'qup-i2c1-default', 'qup-i2c10-default', 'qup-i2c11-default', 'qup-i2c12-default', 'qup-i2c13-default', 'qup-i2c14-default', 'qup-i2c15-default', 'qup-i2c2-default', 'qup-i2c3-default', 'qup-i2c4-default', 'qup-i2c5-default', 'qup-i2c6-default', 'qup-i2c7-default', 'qup-i2c8-default', 'qup-i2c9-default', 'qup-spi0-default', 'qup-spi1-default', 'qup-spi10-default', 'qup-spi11-default', 'qup-spi12-default', 'qup-spi13-default', 'qup-spi14-default', 'qup-spi15-default', 'qup-spi2-default', 'qup-spi3-default', 'qup-spi4-default', 'qup-spi5-default', 'qup-spi6-default', 'qup-spi7-default', 'qup-spi8-defaul
 t', 'qup-spi9-default', 'qup-uart0-default', 'qup-uart1-default', 'qup-uart10-default', 'qup-uart11-default', 'qup-uart12-default', 'qup-uart13-default', 'qup-uart14-default', 'qup-uart15-default', 'qup-uart2-default', 'qup-uart3-default', 'qup-uart4-default', 'qup-uart5-default', 'qup-uart6-default', 'qup-uart7-default', 'qup-uart8-default', 'qup-uart9-default', 'sd-card-det-n', 'sdc2-clk', 'sdc2-cmd', 'sdc2-data' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
	arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dtb
	arch/arm64/boot/dts/qcom/sdm845-mtp.dtb

pinctrl@3400000: 'cci0-default', 'cci0-sleep', 'cci1-default', 'cci1-sleep', 'qspi-clk', 'qspi-cs0', 'qspi-cs1', 'qspi-data01', 'qspi-data12', 'quat_mi2s_active', 'quat_mi2s_sd0_active', 'quat_mi2s_sd0_sleep', 'quat_mi2s_sd1_active', 'quat_mi2s_sd1_sleep', 'quat_mi2s_sd2_active', 'quat_mi2s_sd2_sleep', 'quat_mi2s_sd3_active', 'quat_mi2s_sd3_sleep', 'quat_mi2s_sleep', 'qup-i2c0-default', 'qup-i2c1-default', 'qup-i2c10-default', 'qup-i2c11-default', 'qup-i2c12-default', 'qup-i2c13-default', 'qup-i2c14-default', 'qup-i2c15-default', 'qup-i2c2-default', 'qup-i2c3-default', 'qup-i2c4-default', 'qup-i2c5-default', 'qup-i2c6-default', 'qup-i2c7-default', 'qup-i2c8-default', 'qup-i2c9-default', 'qup-spi0-default', 'qup-spi1-default', 'qup-spi10-default', 'qup-spi11-default', 'qup-spi12-default', 'qup-spi13-default', 'qup-spi14-default', 'qup-spi15-default', 'qup-spi2-default', 'qup-spi3-default', 'qup-spi4-default', 'qup-spi5-default', 'qup-spi6-default', 'qup-spi7-default', 'qup-spi8-defaul
 t', 'qup-spi9-default', 'qup-uart0-default', 'qup-uart1-default', 'qup-uart10-default', 'qup-uart11-default', 'qup-uart12-default', 'qup-uart13-default', 'qup-uart14-default', 'qup-uart15-default', 'qup-uart2-default', 'qup-uart3-default', 'qup-uart4-default', 'qup-uart5-default', 'qup-uart6-default', 'qup-uart7-default', 'qup-uart8-default', 'qup-uart9-default', 'sd-card-det-n', 'sdc2-clk', 'sdc2-cmd', 'sdc2-data', 'thinq-key-default' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
	arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dtb

pinctrl@3400000: 'cci0-default', 'cci0-sleep', 'cci1-default', 'cci1-sleep', 'qspi-clk', 'qspi-cs0', 'qspi-cs1', 'qspi-data01', 'qspi-data12', 'quat_mi2s_active', 'quat_mi2s_sd0_active', 'quat_mi2s_sd0_sleep', 'quat_mi2s_sd1_active', 'quat_mi2s_sd1_sleep', 'quat_mi2s_sd2_active', 'quat_mi2s_sd2_sleep', 'quat_mi2s_sd3_active', 'quat_mi2s_sd3_sleep', 'quat_mi2s_sleep', 'qup-i2c0-default', 'qup-i2c1-default', 'qup-i2c10-default', 'qup-i2c11-default', 'qup-i2c12-default', 'qup-i2c13-default', 'qup-i2c14-default', 'qup-i2c15-default', 'qup-i2c2-default', 'qup-i2c3-default', 'qup-i2c4-default', 'qup-i2c5-default', 'qup-i2c6-default', 'qup-i2c7-default', 'qup-i2c8-default', 'qup-i2c9-default', 'qup-spi0-default', 'qup-spi1-default', 'qup-spi10-default', 'qup-spi11-default', 'qup-spi12-default', 'qup-spi13-default', 'qup-spi14-default', 'qup-spi15-default', 'qup-spi2-default', 'qup-spi3-default', 'qup-spi4-default', 'qup-spi5-default', 'qup-spi6-default', 'qup-spi7-default', 'qup-spi8-defaul
 t', 'qup-spi9-default', 'qup-uart0-default', 'qup-uart1-default', 'qup-uart10-default', 'qup-uart11-default', 'qup-uart12-default', 'qup-uart13-default', 'qup-uart14-default', 'qup-uart15-default', 'qup-uart2-default', 'qup-uart3-default', 'qup-uart4-default', 'qup-uart5-default', 'qup-uart6-default', 'qup-uart7-default', 'qup-uart8-default', 'qup-uart9-default', 'sd-card-det-n', 'sdc2-default', 'wcd_intr_default' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
	arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dtb

pinctrl@3400000: 'cci0-default', 'cci0-sleep', 'cci1-default', 'cci1-sleep', 'qspi-clk', 'qspi-cs0', 'qspi-cs1', 'qspi-data01', 'qspi-data12', 'quat_mi2s_active', 'quat_mi2s_sd0_active', 'quat_mi2s_sd0_sleep', 'quat_mi2s_sd1_active', 'quat_mi2s_sd1_sleep', 'quat_mi2s_sd2_active', 'quat_mi2s_sd2_sleep', 'quat_mi2s_sd3_active', 'quat_mi2s_sd3_sleep', 'quat_mi2s_sleep', 'qup-i2c0-default', 'qup-i2c1-default', 'qup-i2c10-default', 'qup-i2c11-default', 'qup-i2c12-default', 'qup-i2c13-default', 'qup-i2c14-default', 'qup-i2c15-default', 'qup-i2c2-default', 'qup-i2c3-default', 'qup-i2c4-default', 'qup-i2c5-default', 'qup-i2c6-default', 'qup-i2c7-default', 'qup-i2c8-default', 'qup-i2c9-default', 'qup-spi0-default', 'qup-spi1-default', 'qup-spi10-default', 'qup-spi11-default', 'qup-spi12-default', 'qup-spi13-default', 'qup-spi14-default', 'qup-spi15-default', 'qup-spi2-default', 'qup-spi3-default', 'qup-spi4-default', 'qup-spi5-default', 'qup-spi6-default', 'qup-spi7-default', 'qup-spi8-defaul
 t', 'qup-spi9-default', 'qup-uart0-default', 'qup-uart1-default', 'qup-uart10-default', 'qup-uart11-default', 'qup-uart12-default', 'qup-uart13-default', 'qup-uart14-default', 'qup-uart15-default', 'qup-uart2-default', 'qup-uart3-default', 'qup-uart4-default', 'qup-uart5-default', 'qup-uart6-default', 'qup-uart7-default', 'qup-uart8-default', 'qup-uart9-default', 'sde-dsi-active', 'sde-dsi-suspend', 'sde-te-active', 'sde-te-suspend', 'ts-int-active', 'ts-int-suspend', 'ts-reset-active', 'ts-reset-suspend' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
	arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dtb

pinctrl@3400000: 'cci0-default', 'cci0-sleep', 'cci1-default', 'cci1-sleep', 'qspi-clk', 'qspi-cs0', 'qspi-cs1', 'qspi-data01', 'qspi-data12', 'quat_mi2s_active', 'quat_mi2s_sd0_active', 'quat_mi2s_sd0_sleep', 'quat_mi2s_sd1_active', 'quat_mi2s_sd1_sleep', 'quat_mi2s_sd2_active', 'quat_mi2s_sd2_sleep', 'quat_mi2s_sd3_active', 'quat_mi2s_sd3_sleep', 'quat_mi2s_sleep', 'qup-i2c0-default', 'qup-i2c1-default', 'qup-i2c10-default', 'qup-i2c11-default', 'qup-i2c12-default', 'qup-i2c13-default', 'qup-i2c14-default', 'qup-i2c15-default', 'qup-i2c2-default', 'qup-i2c3-default', 'qup-i2c4-default', 'qup-i2c5-default', 'qup-i2c6-default', 'qup-i2c7-default', 'qup-i2c8-default', 'qup-i2c9-default', 'qup-spi0-default', 'qup-spi1-default', 'qup-spi10-default', 'qup-spi11-default', 'qup-spi12-default', 'qup-spi13-default', 'qup-spi14-default', 'qup-spi15-default', 'qup-spi2-default', 'qup-spi3-default', 'qup-spi4-default', 'qup-spi5-default', 'qup-spi6-default', 'qup-spi7-default', 'qup-spi8-defaul
 t', 'qup-spi9-default', 'qup-uart0-default', 'qup-uart1-default', 'qup-uart10-default', 'qup-uart11-default', 'qup-uart12-default', 'qup-uart13-default', 'qup-uart14-default', 'qup-uart15-default', 'qup-uart2-default', 'qup-uart3-default', 'qup-uart4-default', 'qup-uart5-default', 'qup-uart6-default', 'qup-uart7-default', 'qup-uart8-default', 'qup-uart9-default', 'sde-dsi-active', 'sde-dsi-suspend', 'ts-int-default', 'ts-int-sleep', 'ts-reset-default', 'ts-reset-sleep', 'wcd-intr-default' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
	arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dtb

pinctrl@3400000: sdc2-default-state: 'oneOf' conditional failed, one must be fixed:
	arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dtb
	arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dtb
	arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dtb
Krzysztof Kozlowski Oct. 1, 2022, 9:08 a.m. UTC | #2 
On 01/10/2022 00:05, Rob Herring wrote:
> On Fri, 30 Sep 2022 22:05:29 +0200, Krzysztof Kozlowski wrote:
>> Convert Qualcomm SDM845 pin controller bindings to DT schema.  Keep
>> the parsing of pin configuration subnodes consistent with other Qualcomm
>> schemas (children named with '-state' suffix, their children with
>> '-pins').
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> ---
>>  .../bindings/pinctrl/qcom,sdm845-pinctrl.txt  | 176 ------------------
>>  .../bindings/pinctrl/qcom,sdm845-pinctrl.yaml | 158 ++++++++++++++++
>>  2 files changed, 158 insertions(+), 176 deletions(-)
>>  delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
>>  create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml
>>
> 
> Running 'make dtbs_check' with the schema in this patch gives the
> following warnings. Consider if they are expected or the schema is
> incorrect. These may not be new warnings.
> 
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
> 
> Full log is available here: https://patchwork.ozlabs.org/patch/
> 
> 
> pinctrl@3400000: 'ap-edp-bklten', 'ap-suspend-l-hog', 'ap_suspend_l_assert', 'ap_suspend_l_deassert', 'bios-flash-wp-r-l', 'cci0-default', 'cci0-sleep', 'cci1-default', 'cci1-sleep', 'ec-ap-int-l', 'edp-brij-en', 'edp-brij-irq', 'en-pp3300-dx-edp', 'h1-ap-int-odl', 'pen-eject-odl', 'pen-irq-l', 'pen-pdct-l', 'pen-rst-l', 'qspi-clk', 'qspi-cs0', 'qspi-cs1', 'qspi-data01', 'qspi-data12', 'quat_mi2s_active', 'quat_mi2s_sd0_active', 'quat_mi2s_sd0_sleep', 'quat_mi2s_sd1_active', 'quat_mi2s_sd1_sleep', 'quat_mi2s_sd2_active', 'quat_mi2s_sd2_sleep', 'quat_mi2s_sd3_active', 'quat_mi2s_sd3_sleep', 'quat_mi2s_sleep', 'qup-i2c0-default', 'qup-i2c1-default', 'qup-i2c10-default', 'qup-i2c11-default', 'qup-i2c12-default', 'qup-i2c13-default', 'qup-i2c14-default', 'qup-i2c15-default', 'qup-i2c2-default', 'qup-i2c3-default', 'qup-i2c4-default', 'qup-i2c5-default', 'qup-i2c6-default', 'qup-i2c7-default', 'qup-i2c8-default', 'qup-i2c9-default', 'qup-spi0-default', 'qup-spi1-default', 'qup-spi10-default', 'qup-spi11-default', 'qup-spi12-default', 'qup-spi13-default', 'qup-spi14-default', 'qup-spi15-default', 'qup-spi2-default', 'qup-spi3-default', 'qup-spi4-default', 'qup-spi5-default', 'qup-spi6-default', 'qup-spi7-default', 'qup-spi8-default', 'qup-spi9-default', 'qup-uart0-default', 'qup-uart1-default', 'qup-uart10-default', 'qup-uart11-default', 'qup-uart12-default', 'qup-uart13-default', 'qup-uart14-default', 'qup-uart15-default', 'qup-uart2-default', 'qup-uart3-default', 'qup-uart4-default', 'qup-uart5-default', 'qup-uart6-default', 'qup-uart7-default', 'qup-uart8-default', 'qup-uart9-default', 'sd-cd-odl', 'sdc2-clk', 'sdc2-cmd', 'sdc2-data', 'ts-int-l', 'ts-reset-l' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
> 	arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dtb
> 	arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dtb
> 	arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dtb

This is fixed in patch #1 in this set, however for some reason DT
patchwork did not get it (maybe size too big?).

For reference, the patch is available in Qualcomm patchwork:
https://patchwork.kernel.org/project/linux-arm-msm/patch/20220930200529.331223-2-krzysztof.kozlowski@linaro.org/

Best regards,
Krzysztof
Rob Herring (Arm) Oct. 3, 2022, 5:10 p.m. UTC | #3 
On Sat, Oct 01, 2022 at 11:08:58AM +0200, Krzysztof Kozlowski wrote:
> On 01/10/2022 00:05, Rob Herring wrote:
> > On Fri, 30 Sep 2022 22:05:29 +0200, Krzysztof Kozlowski wrote:
> >> Convert Qualcomm SDM845 pin controller bindings to DT schema.  Keep
> >> the parsing of pin configuration subnodes consistent with other Qualcomm
> >> schemas (children named with '-state' suffix, their children with
> >> '-pins').
> >>
> >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >> ---
> >>  .../bindings/pinctrl/qcom,sdm845-pinctrl.txt  | 176 ------------------
> >>  .../bindings/pinctrl/qcom,sdm845-pinctrl.yaml | 158 ++++++++++++++++
> >>  2 files changed, 158 insertions(+), 176 deletions(-)
> >>  delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
> >>  create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml
> >>
> > 
> > Running 'make dtbs_check' with the schema in this patch gives the
> > following warnings. Consider if they are expected or the schema is
> > incorrect. These may not be new warnings.
> > 
> > Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> > This will change in the future.
> > 
> > Full log is available here: https://patchwork.ozlabs.org/patch/
> > 
> > 
> > pinctrl@3400000: 'ap-edp-bklten', 'ap-suspend-l-hog', 'ap_suspend_l_assert', 'ap_suspend_l_deassert', 'bios-flash-wp-r-l', 'cci0-default', 'cci0-sleep', 'cci1-default', 'cci1-sleep', 'ec-ap-int-l', 'edp-brij-en', 'edp-brij-irq', 'en-pp3300-dx-edp', 'h1-ap-int-odl', 'pen-eject-odl', 'pen-irq-l', 'pen-pdct-l', 'pen-rst-l', 'qspi-clk', 'qspi-cs0', 'qspi-cs1', 'qspi-data01', 'qspi-data12', 'quat_mi2s_active', 'quat_mi2s_sd0_active', 'quat_mi2s_sd0_sleep', 'quat_mi2s_sd1_active', 'quat_mi2s_sd1_sleep', 'quat_mi2s_sd2_active', 'quat_mi2s_sd2_sleep', 'quat_mi2s_sd3_active', 'quat_mi2s_sd3_sleep', 'quat_mi2s_sleep', 'qup-i2c0-default', 'qup-i2c1-default', 'qup-i2c10-default', 'qup-i2c11-default', 'qup-i2c12-default', 'qup-i2c13-default', 'qup-i2c14-default', 'qup-i2c15-default', 'qup-i2c2-default', 'qup-i2c3-default', 'qup-i2c4-default', 'qup-i2c5-default', 'qup-i2c6-default', 'qup-i2c7-default', 'qup-i2c8-default', 'qup-i2c9-default', 'qup-spi0-default', 'qup-spi1-default', 'qup-spi10-default', 'qup-spi11-default', 'qup-spi12-default', 'qup-spi13-default', 'qup-spi14-default', 'qup-spi15-default', 'qup-spi2-default', 'qup-spi3-default', 'qup-spi4-default', 'qup-spi5-default', 'qup-spi6-default', 'qup-spi7-default', 'qup-spi8-default', 'qup-spi9-default', 'qup-uart0-default', 'qup-uart1-default', 'qup-uart10-default', 'qup-uart11-default', 'qup-uart12-default', 'qup-uart13-default', 'qup-uart14-default', 'qup-uart15-default', 'qup-uart2-default', 'qup-uart3-default', 'qup-uart4-default', 'qup-uart5-default', 'qup-uart6-default', 'qup-uart7-default', 'qup-uart8-default', 'qup-uart9-default', 'sd-cd-odl', 'sdc2-clk', 'sdc2-cmd', 'sdc2-data', 'ts-int-l', 'ts-reset-l' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
> > 	arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dtb
> > 	arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dtb
> > 	arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dtb
> 
> This is fixed in patch #1 in this set, however for some reason DT
> patchwork did not get it (maybe size too big?).

PW is filtered to only bindings, binding headers, and drivers/of/.

Rob
Rob Herring (Arm) Oct. 3, 2022, 5:11 p.m. UTC | #4 
On Fri, 30 Sep 2022 22:05:29 +0200, Krzysztof Kozlowski wrote:
> Convert Qualcomm SDM845 pin controller bindings to DT schema.  Keep
> the parsing of pin configuration subnodes consistent with other Qualcomm
> schemas (children named with '-state' suffix, their children with
> '-pins').
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
>  .../bindings/pinctrl/qcom,sdm845-pinctrl.txt  | 176 ------------------
>  .../bindings/pinctrl/qcom,sdm845-pinctrl.yaml | 158 ++++++++++++++++
>  2 files changed, 158 insertions(+), 176 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>
Krzysztof Kozlowski Oct. 17, 2022, 10:42 p.m. UTC | #5 
On Fri, 30 Sep 2022 22:05:29 +0200, Krzysztof Kozlowski wrote:
> Convert Qualcomm SDM845 pin controller bindings to DT schema.  Keep
> the parsing of pin configuration subnodes consistent with other Qualcomm
> schemas (children named with '-state' suffix, their children with
> '-pins').
> 
> 

Applied, thanks!

[2/2] dt-bindings: pinctrl: qcom,sdm845: convert to dtschema
      https://git.kernel.org/krzk/linux-dt/c/dba79c34605d60cb02c2951c701ea0bc16937153

Best regards,
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
deleted file mode 100644
index 7462e3743c68..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
+++ /dev/null
@@ -1,176 +0,0 @@ 
-Qualcomm SDM845 TLMM block
-
-This binding describes the Top Level Mode Multiplexer block found in the
-SDM845 platform.
-
-- compatible:
-	Usage: required
-	Value type: <string>
-	Definition: must be "qcom,sdm845-pinctrl"
-
-- reg:
-	Usage: required
-	Value type: <prop-encoded-array>
-	Definition: the base address and size of the TLMM register space.
-
-- interrupts:
-	Usage: required
-	Value type: <prop-encoded-array>
-	Definition: should specify the TLMM summary IRQ.
-
-- interrupt-controller:
-	Usage: required
-	Value type: <none>
-	Definition: identifies this node as an interrupt controller
-
-- #interrupt-cells:
-	Usage: required
-	Value type: <u32>
-	Definition: must be 2. Specifying the pin number and flags, as defined
-		    in <dt-bindings/interrupt-controller/irq.h>
-
-- gpio-controller:
-	Usage: required
-	Value type: <none>
-	Definition: identifies this node as a gpio controller
-
-- #gpio-cells:
-	Usage: required
-	Value type: <u32>
-	Definition: must be 2. Specifying the pin number and flags, as defined
-		    in <dt-bindings/gpio/gpio.h>
-
-Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
-a general description of GPIO and interrupt bindings.
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-The pin configuration nodes act as a container for an arbitrary number of
-subnodes. Each of these subnodes represents some desired configuration for a
-pin, a group, or a list of pins or groups. This configuration can include the
-mux function to select on those pin(s)/group(s), and various pin configuration
-parameters, such as pull-up, drive strength, etc.
-
-
-PIN CONFIGURATION NODES:
-
-The name of each subnode is not important; all subnodes should be enumerated
-and processed purely based on their content.
-
-Each subnode only affects those parameters that are explicitly listed. In
-other words, a subnode that lists a mux function but no pin configuration
-parameters implies no information about any pin configuration parameters.
-Similarly, a pin subnode that describes a pullup parameter implies no
-information about e.g. the mux function.
-
-
-The following generic properties as defined in pinctrl-bindings.txt are valid
-to specify in a pin configuration subnode:
-
-- pins:
-	Usage: required
-	Value type: <string-array>
-	Definition: List of gpio pins affected by the properties specified in
-		    this subnode.
-
-		    Valid pins are:
-		      gpio0-gpio149
-		        Supports mux, bias and drive-strength
-
-		      sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset
-		        Supports bias and drive-strength
-
-- function:
-	Usage: required
-	Value type: <string>
-	Definition: Specify the alternative function to be configured for the
-		    specified pins. Functions are only valid for gpio pins.
-		    Valid values are:
-
-		    gpio, adsp_ext, agera_pll, atest_char, atest_tsens,
-		    atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
-		    atest_usb12, atest_usb13, atest_usb2, atest_usb20,
-		    atest_usb21, atest_usb22, atest_usb23, audio_ref,
-		    btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
-		    cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
-		    cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
-		    ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1,
-		    gcc_gp2, gcc_gp3, jitter_bist, ldo_en, ldo_update,
-		    lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1,
-		    mdp_vsync2, mdp_vsync3, mss_lte, nav_pps, pa_indicator,
-		    pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl,
-		    pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti,
-		    qdss, qlink_enable, qlink_request, qua_mi2s, qup0, qup1,
-		    qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3, qup4,
-		    qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6,
-		    qspi_clk, qspi_cs, qspi_data, sd_write, sdc4_clk, sdc4_cmd,
-		    sdc4_data, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu_ch0,
-		    tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2,
-		    tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync,
-		    tsif2_clk, tsif2_data, tsif2_en, tsif2_error, tsif2_sync,
-		    uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
-		    uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy,
-		    vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0,
-		    wlan2_adc1,
-
-- bias-disable:
-	Usage: optional
-	Value type: <none>
-	Definition: The specified pins should be configured as no pull.
-
-- bias-pull-down:
-	Usage: optional
-	Value type: <none>
-	Definition: The specified pins should be configured as pull down.
-
-- bias-pull-up:
-	Usage: optional
-	Value type: <none>
-	Definition: The specified pins should be configured as pull up.
-
-- output-high:
-	Usage: optional
-	Value type: <none>
-	Definition: The specified pins are configured in output mode, driven
-		    high.
-		    Not valid for sdc pins.
-
-- output-low:
-	Usage: optional
-	Value type: <none>
-	Definition: The specified pins are configured in output mode, driven
-		    low.
-		    Not valid for sdc pins.
-
-- drive-strength:
-	Usage: optional
-	Value type: <u32>
-	Definition: Selects the drive strength for the specified pins, in mA.
-		    Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
-
-Example:
-
-	tlmm: pinctrl@3400000 {
-		compatible = "qcom,sdm845-pinctrl";
-		reg = <0x03400000 0xc00000>;
-		interrupts = <GIC_SPI 208 0>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-
-		qup9_active: qup9-active {
-			mux {
-				pins = "gpio4", "gpio5";
-				function = "qup9";
-			};
-
-			config {
-				pins = "gpio4", "gpio5";
-				drive-strength = <2>;
-				bias-disable;
-			};
-		};
-	};
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml
new file mode 100644
index 000000000000..da0ef5698f3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml
@@ -0,0 +1,158 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sdm845-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SDM845 TLMM pin controller
+
+maintainers:
+  - Bjorn Andersson <andersson@kernel.org>
+  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description:
+  Top Level Mode Multiplexer pin controller node in Qualcomm SDM845 SoC.
+
+allOf:
+  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,sdm845-pinctrl
+
+  reg:
+    maxItems: 1
+
+  interrupts: true
+  interrupt-controller: true
+  "#interrupt-cells": true
+  gpio-controller: true
+
+  gpio-reserved-ranges:
+    minItems: 1
+    maxItems: 75
+
+  gpio-line-names:
+    maxItems: 150
+
+  "#gpio-cells": true
+  gpio-ranges: true
+  wakeup-parent: true
+
+patternProperties:
+  "-state$":
+    oneOf:
+      - $ref: "#/$defs/qcom-sdm845-tlmm-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-sdm845-tlmm-state"
+        additionalProperties: false
+
+$defs:
+  qcom-sdm845-tlmm-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+
+    properties:
+      pins:
+        description:
+          List of gpio pins affected by the properties specified in this
+          subnode.
+        items:
+          oneOf:
+            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
+            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
+        minItems: 1
+        maxItems: 36
+
+      function:
+        description:
+          Specify the alternative function to be configured for the specified
+          pins.
+        enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2,
+                atest_usb1, atest_usb10, atest_usb11, atest_usb12, atest_usb13,
+                atest_usb2, atest_usb20, atest_usb21, atest_usb22, atest_usb23,
+                audio_ref, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
+                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
+                cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
+                ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1,
+                gcc_gp2, gcc_gp3, gpio, jitter_bist, ldo_en, ldo_update,
+                lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
+                mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator, pci_e0,
+                pci_e1, phase_flag, pll_bist, pll_bypassnl, pll_reset,
+                pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable,
+                qlink_request, qspi_clk, qspi_cs, qspi_data, qua_mi2s, qup0,
+                qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3,
+                qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6,
+                sdc4_clk, sdc4_cmd, sdc4_data, sd_write, sec_mi2s, sp_cmu,
+                spkr_i2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
+                tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
+                tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
+                tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
+                uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
+                uim_batt, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
+                wlan1_adc1, wlan2_adc0, wlan2_adc1]
+
+      bias-disable: true
+      bias-pull-down: true
+      bias-pull-up: true
+      drive-strength: true
+      input-enable: true
+      output-high: true
+      output-low: true
+
+    required:
+      - pins
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    pinctrl@3400000 {
+        compatible = "qcom,sdm845-pinctrl";
+        reg = <0x03400000 0xc00000>;
+        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        gpio-ranges = <&tlmm 0 0 151>;
+        wakeup-parent = <&pdc_intc>;
+
+        cci0-default-state {
+            pins = "gpio17", "gpio18";
+            function = "cci_i2c";
+
+            bias-pull-up;
+            drive-strength = <2>;
+        };
+
+        cam0-default-state {
+            rst-pins {
+                pins = "gpio9";
+                function = "gpio";
+
+                drive-strength = <16>;
+                bias-disable;
+            };
+
+            mclk0-pins {
+                pins = "gpio13";
+                function = "cam_mclk";
+
+                drive-strength = <16>;
+                bias-disable;
+            };
+        };
+    };