Message ID | 20220925105124.82033-4-richard.henderson@linaro.org |
---|---|
State | Superseded |
Headers | show |
Series | tcg: CPUTLBEntryFull and TARGET_TB_PCREL | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > When PAGE_WRITE_INV is set when calling tlb_set_page, > we immediately set TLB_INVALID_MASK in order to force > tlb_fill to be called on the next lookup. Here in > probe_access_internal, we have just called tlb_fill > and eliminated true misses, thus the lookup must be valid. > > This allows us to remove a warning comment from s390x. > There doesn't seem to be a reason to change the code though. > > Cc: David Hildenbrand <david@redhat.com> > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
On 25.09.22 12:51, Richard Henderson wrote: > When PAGE_WRITE_INV is set when calling tlb_set_page, > we immediately set TLB_INVALID_MASK in order to force > tlb_fill to be called on the next lookup. Here in > probe_access_internal, we have just called tlb_fill > and eliminated true misses, thus the lookup must be valid. > > This allows us to remove a warning comment from s390x. > There doesn't seem to be a reason to change the code though. > > Cc: David Hildenbrand <david@redhat.com> > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- Reviewed-by: David Hildenbrand <david@redhat.com>
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 03395e725d..91f2b53142 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1535,6 +1535,7 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, } tlb_addr = tlb_read_ofs(entry, elt_ofs); + flags = TLB_FLAGS_MASK; page_addr = addr & TARGET_PAGE_MASK; if (!tlb_hit_page(tlb_addr, page_addr)) { if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) { @@ -1550,10 +1551,17 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, /* TLB resize via tlb_fill may have moved the entry. */ entry = tlb_entry(env, mmu_idx, addr); + + /* + * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately, + * to force the next access through tlb_fill. We've just + * called tlb_fill, so we know that this entry *is* valid. + */ + flags &= ~TLB_INVALID_MASK; } tlb_addr = tlb_read_ofs(entry, elt_ofs); } - flags = tlb_addr & TLB_FLAGS_MASK; + flags &= tlb_addr; /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index fc52aa128b..3758b9e688 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -148,10 +148,6 @@ static int s390_probe_access(CPUArchState *env, target_ulong addr, int size, #else int flags; - /* - * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr==NULL - * to detect if there was an exception during tlb_fill(). - */ env->tlb_fill_exc = 0; flags = probe_access_flags(env, addr, access_type, mmu_idx, nonfault, phost, ra);