| Message ID | 20220915181558.354737-9-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for Renesas RZ/Five SoC | expand |
On 15/09/2022 23:41, Lad, Prabhakar wrote: > Hi Conor, > > Thank you for the review. > > On Thu, Sep 15, 2022 at 10:56 PM <Conor.Dooley@microchip.com> wrote: >> >> On 15/09/2022 19:15, Prabhakar wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>> >>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> >>> >>> Enable the minimal blocks required for booting the Renesas RZ/Five >>> SMARC EVK with initramfs. >>> >>> Below are the blocks enabled: >>> - CPG >>> - CPU0 >>> - DDR (memory regions) >>> - PINCTRL >>> - PLIC >>> - SCIF0 >>> >>> Note we have deleted the nodes from the DT for which support needs to be >>> added for RZ/Five SoC and are enabled by RZ/G2UL SMARC EVK SoM/carrier >>> board DTS/I. >> >> idk, I am not sure what to think of this approach. >> >> What do you mean by "for which support needs to be added"? If the support >> does not exist yet, then is surely you can just add the nodes and it will >> be fine? >> > As pointed out previously, I am re-using the below files [1] (SoM) and > [2] (Carrier board) as the RZ/Five SMARC EVK is pin compatible. Since > [1] and [2] enable almost all the peripherals (status = okay) on the > RZ/G2UL SMARC EVK which are supported. For example [1] enables SDHI0/1 > this high speed block needs DMA and without cache management fixed on > Andes core we cannot enable this on RZ/Five SoC so currently a > placeholder is added for it in the RZ/FIve SoC DTSI and is deleted in > the board DTS file. > > Below blocks suffer the cache management issue: > - DMAC > - ETH > - SDHI > - USB > > Rest of the blocks will be gradually enabled (as soon as this initial > patchset is merged) along with the DT binding doc updates. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?h=v6.0-rc5 > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?h=v6.0-rc5 Explanations are reasonable, but again - that information is important and really needs to be included in the commit message etc. Thanks, Conor.
Hi Geert, Thank you for the review. On Tue, Sep 20, 2022 at 1:32 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Thu, Sep 15, 2022 at 8:17 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Enable the minimal blocks required for booting the Renesas RZ/Five > > SMARC EVK with initramfs. > > > > Below are the blocks enabled: > > - CPG > > - CPU0 > > - DDR (memory regions) > > - PINCTRL > > - PLIC > > - SCIF0 > > > > Note we have deleted the nodes from the DT for which support needs to be > > added for RZ/Five SoC and are enabled by RZ/G2UL SMARC EVK SoM/carrier > > board DTS/I. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > v2->v3 > > * Dropped RB tags from Conor and Geert > > * Now re-using the SoM and carrier board DTS/I from RZ/G2UL > > Thanks for the update! > > > --- /dev/null > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts > > @@ -0,0 +1,27 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +/* > > + * Device Tree Source for the RZ/Five SMARC EVK > > + * > > + * Copyright (C) 2022 Renesas Electronics Corp. > > + */ > > + > > +/dts-v1/; > > + > > +/* > > + * DIP-Switch SW1 setting > > + * 1 : High; 0: Low > > + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) > > + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1) > > + * Please change below macros according to SW1 setting on SoM > > "on the SoM" (like in r9a07g043u11-smarc.dts)? > Agreed, I will update it. > > --- /dev/null > > +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi > > @@ -0,0 +1,42 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +/* > > + * Device Tree Source for the RZ/Five SMARC EVK SOM > > + * > > + * Copyright (C) 2022 Renesas Electronics Corp. > > + */ > > + > > +#include <arm64/renesas/rzg2ul-smarc-som.dtsi> > > + > > +/ { > > + aliases { > > + /delete-property/ ethernet0; > > + /delete-property/ ethernet1; > > OK > I assume you are OK with dropping the above too? > > + }; > > + > > + chosen { > > + bootargs = "ignore_loglevel"; > > + }; > > +}; > > + > > +#if (SW_SW0_DEV_SEL) > > +/delete-node/ &adc; > > +#endif > > + > > +#if (!SW_ET0_EN_N) > > +/delete-node/ ð0; > > +#endif > > +/delete-node/ ð1; > > + > > +/delete-node/ &ostm1; > > +/delete-node/ &ostm2; > > Given they are all placeholders, do you really need to delete them? > (more below) > I did retest without deleting the place holders and I dont see any issues (or splat) while booting up so I'll drop them while sending the v4. Cheers, Prabhakar
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index ff174996cdfd..b0ff5fbabb0c 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -3,5 +3,6 @@ subdir-y += sifive subdir-y += starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan subdir-y += microchip +subdir-y += renesas obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile new file mode 100644 index 000000000000..2d3f5751a649 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts new file mode 100644 index 000000000000..9747f30c5db5 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; + +/* + * DIP-Switch SW1 setting + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1) + * Please change below macros according to SW1 setting on SoM + */ +#define SW_SW0_DEV_SEL 1 +#define SW_ET0_EN_N 1 + +#include "r9a07g043.dtsi" +#include "rzfive-smarc-som.dtsi" +#include "rzfive-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g043f01"; + compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043"; +}; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi new file mode 100644 index 000000000000..8547c273f140 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK SOM + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <arm64/renesas/rzg2ul-smarc-som.dtsi> + +/ { + aliases { + /delete-property/ ethernet0; + /delete-property/ ethernet1; + }; + + chosen { + bootargs = "ignore_loglevel"; + }; +}; + +#if (SW_SW0_DEV_SEL) +/delete-node/ &adc; +#endif + +#if (!SW_ET0_EN_N) +/delete-node/ ð0; +#endif +/delete-node/ ð1; + +/delete-node/ &ostm1; +/delete-node/ &ostm2; + +/delete-node/ ®_1p8v; +/delete-node/ ®_3p3v; + +/delete-node/ &sdhi0; + +#if !(SW_SW0_DEV_SEL) +/delete-node/ &vccq_sdhi0; +#endif + +/delete-node/ &wdt0; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi new file mode 100644 index 000000000000..3fde7192241e --- /dev/null +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK carrier board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <arm64/renesas/rzg2ul-smarc.dtsi> + +/ { + aliases { + /delete-property/ i2c0; + /delete-property/ i2c1; + }; +}; + +/delete-node/ &audio_clk1; +/delete-node/ &audio_clk2; +/delete-node/ &audio_mclock; + +/delete-node/ &canfd; + +/delete-node/ &cpu_dai; + +/delete-node/ &ehci0; +/delete-node/ &ehci1; + +/delete-node/ &hsusb; + +/delete-node/ &i2c0; +/delete-node/ &i2c1; + +/delete-node/ &ohci0; +/delete-node/ &ohci1; + +&pinctrl { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; +}; + +/delete-node/ &phyrst; + +/delete-node/ &sdhi1; + +/delete-node/ &snd_rzg2l; + +/delete-node/ &spi1; + +/delete-node/ &ssi1; + +/delete-node/ &usb0_vbus_otg; + +/delete-node/ &usb2_phy0; +/delete-node/ &usb2_phy1; + +/delete-node/ &vccq_sdhi1;