| Message ID | 20220901044149.16782-1-rex-bc.chen@mediatek.com |
|---|---|
| Headers | show |
| Series | Add MT8195 DisplayPort driver | expand |
Il 01/09/22 06:41, Bo-Chen Chen ha scritto: > This patch is separated from v10 which is including dp driver, phy driver > and dpintf driver. This series is only contained the DisplayPort driver. For the entire series: Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Thanks! Angelo > > Bo-Chen Chen (4): > drm/mediatek: dp: Add multiple bridge types support > drm/mediatek: dp: Add multiple smc commands support > drm/mediatek: dp: Add multiple calibration data formats support > drm/mediatek: dp: Determine device of next_bridge > > Guillaume Ranquet (2): > drm/mediatek: dp: Add MT8195 External DisplayPort support > drm/mediatek: dp: Audio support for MT8195 > > Jitao Shi (1): > drm/mediatek: dp: Add hpd debounce > > Markus Schneider-Pargmann (3): > dt-bindings: mediatek,dp: Add Display Port binding > video/hdmi: Add audio_infoframe packing for DP > drm/mediatek: Add MT8195 Embedded DisplayPort driver > > .../display/mediatek/mediatek,dp.yaml | 116 + > drivers/gpu/drm/mediatek/Kconfig | 9 + > drivers/gpu/drm/mediatek/Makefile | 2 + > drivers/gpu/drm/mediatek/mtk_dp.c | 2661 +++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_dp_reg.h | 356 +++ > drivers/video/hdmi.c | 82 +- > include/drm/display/drm_dp.h | 2 + > include/linux/hdmi.h | 7 +- > 8 files changed, 3215 insertions(+), 20 deletions(-) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.c > create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_reg.h >
Hi, Bo-Chen: On Thu, 2022-09-01 at 12:41 +0800, Bo-Chen Chen wrote: > The bridge types of eDP and DP are different. We add device data to > this driver and add bridge_type to the device data to define them. Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_dp.c | 16 ++++++++++++++-- > 1 file changed, 14 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c > b/drivers/gpu/drm/mediatek/mtk_dp.c > index e2ec9b02b1aa..2696c1ac1a47 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dp.c > +++ b/drivers/gpu/drm/mediatek/mtk_dp.c > @@ -101,6 +101,7 @@ struct mtk_dp { > struct drm_device *drm_dev; > struct drm_dp_aux aux; > > + const struct mtk_dp_data *data; > struct mtk_dp_info info; > struct mtk_dp_train_info train_info; > > @@ -109,6 +110,9 @@ struct mtk_dp { > struct regmap *regs; > }; > > +struct mtk_dp_data { > + int bridge_type; > +}; > static const struct mtk_dp_efuse_fmt > mtk_dp_efuse_data[MTK_DP_CAL_MAX] = { > [MTK_DP_CAL_GLB_BIAS_TRIM] = { > .idx = 3, > @@ -1871,6 +1875,7 @@ static int mtk_dp_probe(struct platform_device > *pdev) > return -ENOMEM; > > mtk_dp->dev = dev; > + mtk_dp->data = (struct mtk_dp_data > *)of_device_get_match_data(dev); > > irq_num = platform_get_irq(pdev, 0); > if (irq_num < 0) > @@ -1925,7 +1930,7 @@ static int mtk_dp_probe(struct platform_device > *pdev) > > mtk_dp->bridge.ops = > DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | > DRM_BRIDGE_OP_HPD; > - mtk_dp->bridge.type = DRM_MODE_CONNECTOR_eDP; > + mtk_dp->bridge.type = mtk_dp->data->bridge_type; > > drm_bridge_add(&mtk_dp->bridge); > > @@ -1974,8 +1979,15 @@ static int mtk_dp_resume(struct device *dev) > > static SIMPLE_DEV_PM_OPS(mtk_dp_pm_ops, mtk_dp_suspend, > mtk_dp_resume); > > +static const struct mtk_dp_data mt8195_edp_data = { > + .bridge_type = DRM_MODE_CONNECTOR_eDP, > +}; > + > static const struct of_device_id mtk_dp_of_match[] = { > - { .compatible = "mediatek,mt8195-edp-tx" }, > + { > + .compatible = "mediatek,mt8195-edp-tx", > + .data = &mt8195_edp_data, > + }, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_dp_of_match);
Hi, Bo-Chen: On Thu, 2022-09-01 at 12:41 +0800, Bo-Chen Chen wrote: > The calibration data formats of eDP and DP are different. We add > "const struct mtk_dp_efuse_fmt *efuse_fmt" to the device data to > define them. Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_dp.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c > b/drivers/gpu/drm/mediatek/mtk_dp.c > index 971bd744cdb2..136e13150281 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dp.c > +++ b/drivers/gpu/drm/mediatek/mtk_dp.c > @@ -113,8 +113,10 @@ struct mtk_dp { > struct mtk_dp_data { > int bridge_type; > unsigned int smc_cmd; > + const struct mtk_dp_efuse_fmt *efuse_fmt; > }; > -static const struct mtk_dp_efuse_fmt > mtk_dp_efuse_data[MTK_DP_CAL_MAX] = { > + > +static const struct mtk_dp_efuse_fmt > mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = { > [MTK_DP_CAL_GLB_BIAS_TRIM] = { > .idx = 3, > .shift = 27, > @@ -811,7 +813,7 @@ static void mtk_dp_get_calibration_data(struct > mtk_dp *mtk_dp) > } > > for (i = 0; i < MTK_DP_CAL_MAX; i++) { > - fmt = &mtk_dp_efuse_data[i]; > + fmt = &mtk_dp->data->efuse_fmt[i]; > cal_data[i] = (buf[fmt->idx] >> fmt->shift) & fmt- > >mask; > > if (cal_data[i] < fmt->min_val || cal_data[i] > fmt- > >max_val) { > @@ -827,7 +829,7 @@ static void mtk_dp_get_calibration_data(struct > mtk_dp *mtk_dp) > use_default_val: > dev_warn(mtk_dp->dev, "Use default calibration data\n"); > for (i = 0; i < MTK_DP_CAL_MAX; i++) > - cal_data[i] = mtk_dp_efuse_data[i].default_val; > + cal_data[i] = mtk_dp->data->efuse_fmt[i].default_val; > } > > static void mtk_dp_set_calibration_data(struct mtk_dp *mtk_dp) > @@ -1983,6 +1985,7 @@ static SIMPLE_DEV_PM_OPS(mtk_dp_pm_ops, > mtk_dp_suspend, mtk_dp_resume); > static const struct mtk_dp_data mt8195_edp_data = { > .bridge_type = DRM_MODE_CONNECTOR_eDP, > .smc_cmd = MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE, > + .efuse_fmt = mt8195_edp_efuse_fmt, > }; > > static const struct of_device_id mtk_dp_of_match[] = {
Hi, Bo-Chen: On Thu, 2022-09-01 at 12:41 +0800, Bo-Chen Chen wrote: > From: Guillaume Ranquet <granquet@baylibre.com> > > Add External DisplayPort support to the MT8195 eDP driver. > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_dp.c | 139 > ++++++++++++++++++++++++++++++ > 1 file changed, 139 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c > b/drivers/gpu/drm/mediatek/mtk_dp.c > index e37c9185e4ec..11a94927c0d0 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dp.c > +++ b/drivers/gpu/drm/mediatek/mtk_dp.c > @@ -35,6 +35,7 @@ > > #define MTK_DP_SIP_CONTROL_AARCH32 MTK_SIP_SMC_CMD(0x523) > #define MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE (BIT(0) | BIT(5)) > +#define MTK_DP_SIP_ATF_VIDEO_UNMUTE BIT(5) > > #define MTK_DP_THREAD_CABLE_STATE_CHG BIT(0) > #define MTK_DP_THREAD_HPD_EVENT BIT(1) > @@ -199,6 +200,89 @@ static const struct mtk_dp_efuse_fmt > mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = { > }, > }; > > +static const struct mtk_dp_efuse_fmt > mt8195_dp_efuse_fmt[MTK_DP_CAL_MAX] = { > + [MTK_DP_CAL_GLB_BIAS_TRIM] = { > + .idx = 0, > + .shift = 27, > + .mask = 0x1f, > + .min_val = 1, > + .max_val = 0x1e, > + .default_val = 0xf, > + }, > + [MTK_DP_CAL_CLKTX_IMPSE] = { > + .idx = 0, > + .shift = 13, > + .mask = 0xf, > + .min_val = 1, > + .max_val = 0xe, > + .default_val = 0x8, > + }, > + [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_0] = { > + .idx = 1, > + .shift = 28, > + .mask = 0xf, > + .min_val = 1, > + .max_val = 0xe, > + .default_val = 0x8, > + }, > + [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_1] = { > + .idx = 1, > + .shift = 20, > + .mask = 0xf, > + .min_val = 1, > + .max_val = 0xe, > + .default_val = 0x8, > + }, > + [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_2] = { > + .idx = 1, > + .shift = 12, > + .mask = 0xf, > + .min_val = 1, > + .max_val = 0xe, > + .default_val = 0x8, > + }, > + [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_3] = { > + .idx = 1, > + .shift = 4, > + .mask = 0xf, > + .min_val = 1, > + .max_val = 0xe, > + .default_val = 0x8, > + }, > + [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_0] = { > + .idx = 1, > + .shift = 24, > + .mask = 0xf, > + .min_val = 1, > + .max_val = 0xe, > + .default_val = 0x8, > + }, > + [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_1] = { > + .idx = 1, > + .shift = 16, > + .mask = 0xf, > + .min_val = 1, > + .max_val = 0xe, > + .default_val = 0x8, > + }, > + [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_2] = { > + .idx = 1, > + .shift = 8, > + .mask = 0xf, > + .min_val = 1, > + .max_val = 0xe, > + .default_val = 0x8, > + }, > + [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_3] = { > + .idx = 1, > + .shift = 0, > + .mask = 0xf, > + .min_val = 1, > + .max_val = 0xe, > + .default_val = 0x8, > + }, > +}; > + > static struct regmap_config mtk_dp_regmap_config = { > .reg_bits = 32, > .val_bits = 32, > @@ -1479,6 +1563,50 @@ static int mtk_dp_dt_parse(struct mtk_dp > *mtk_dp, > return 0; > } > > +static enum drm_connector_status mtk_dp_bdg_detect(struct drm_bridge > *bridge) > +{ > + struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge); > + enum drm_connector_status ret = connector_status_disconnected; > + bool enabled = mtk_dp->enabled; > + u8 sink_count = 0; > + > + if (mtk_dp->train_info.cable_plugged_in) { I would modify this as below when I apply this patch into my tree: if (!mtk_dp->train_info.cable_plugged_in) return ret; Reviewed-by: CK Hu <ck.hu@mediatek.com> > + if (!enabled) { > + /* power on aux */ > + mtk_dp_update_bits(mtk_dp, > MTK_DP_TOP_PWR_STATE, > + DP_PWR_STATE_BANDGAP_TPLL_LA > NE, > + DP_PWR_STATE_MASK); > + > + /* power on panel */ > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, > DP_SET_POWER_D0); > + usleep_range(2000, 5000); > + } > + /* > + * Some dongles still source HPD when they do not > connect to any > + * sink device. To avoid this, we need to read the sink > count > + * to make sure we do connect to sink devices. After > this detect > + * function, we just need to check the HPD connection > to check > + * whether we connect to a sink device. > + */ > + drm_dp_dpcd_readb(&mtk_dp->aux, DP_SINK_COUNT, > &sink_count); > + if (DP_GET_SINK_COUNT(sink_count)) > + ret = connector_status_connected; > + > + if (!enabled) { > + /* power off panel */ > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, > DP_SET_POWER_D3); > + usleep_range(2000, 3000); > + > + /* power off aux */ > + mtk_dp_update_bits(mtk_dp, > MTK_DP_TOP_PWR_STATE, > + DP_PWR_STATE_BANDGAP_TPLL, > + DP_PWR_STATE_MASK); > + } > + } > + > + return ret; > +} > + > static struct edid *mtk_dp_get_edid(struct drm_bridge *bridge, > struct drm_connector *connector) > { > @@ -1865,6 +1993,7 @@ static const struct drm_bridge_funcs > mtk_dp_bridge_funcs = { > .atomic_disable = mtk_dp_bridge_atomic_disable, > .mode_valid = mtk_dp_bridge_mode_valid, > .get_edid = mtk_dp_get_edid, > + .detect = mtk_dp_bdg_detect, > }; > > static int mtk_dp_probe(struct platform_device *pdev) > @@ -1991,11 +2120,21 @@ static const struct mtk_dp_data > mt8195_edp_data = { > .efuse_fmt = mt8195_edp_efuse_fmt, > }; > > +static const struct mtk_dp_data mt8195_dp_data = { > + .bridge_type = DRM_MODE_CONNECTOR_DisplayPort, > + .smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE, > + .efuse_fmt = mt8195_dp_efuse_fmt, > +}; > + > static const struct of_device_id mtk_dp_of_match[] = { > { > .compatible = "mediatek,mt8195-edp-tx", > .data = &mt8195_edp_data, > }, > + { > + .compatible = "mediatek,mt8195-dp-tx", > + .data = &mt8195_dp_data, > + }, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_dp_of_match);
Hi, Bo-Chen: On Thu, 2022-09-01 at 12:41 +0800, Bo-Chen Chen wrote: > From: Guillaume Ranquet <granquet@baylibre.com> > > This patch adds audio support to the DP driver for MT8195 with up to > 8 > channels. > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_dp.c | 482 > +++++++++++++++++++++++++- > drivers/gpu/drm/mediatek/mtk_dp_reg.h | 51 +++ > 2 files changed, 532 insertions(+), 1 deletion(-) > > [snip] > +#define MTK_DP_ENC0_P0_308C 0x308c > +#define CH_STATUS_0_DP_ENC0_P0_MASK GENMASK(15, 0) > +#define MTK_DP_ENC0_P0_3090 0x3090 > +#define CH_STATUS_1_DP_ENC0_P0_MASK GENMASK(15, 0) > +#define MTK_DP_ENC0_P0_3094 0x3094 > +#define CH_STATUS_2_DP_ENC0_P0_MASK GENMASK(7, 0) > +#define MTK_DP_ENC0_P0_30A0 0x30a0 Useless, so drop it. Regards, CK > +#define DP_ENC0_30A0_MASK (BIT(7) | > BIT(8) | BIT(12)) > +#define MTK_DP_ENC0_P0_30A4 0x30a4 > +#define AU_TS_CFG_DP_ENC0_P0_MASK GENMASK(7, 0) > +#define MTK_DP_ENC0_P0_30A8 0x30a8 >
01.09.2022 07:41, Bo-Chen Chen пишет: > diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h > index 9e3aff7e68bb..6c0871164771 100644 > --- a/include/drm/display/drm_dp.h > +++ b/include/drm/display/drm_dp.h > @@ -1536,6 +1536,8 @@ enum drm_dp_phy { > #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */ > /* 0x80+ CEA-861 infoframe types */ > > +#define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b Is there any good reason why this is not grouped with the rest of the DP_SDP_* defines above?