| Message ID | 20220822130333.5353-1-shubhrajyoti.datta@amd.com |
|---|---|
| Headers | show |
| Series | serial: pl011: Add xilinx uart | expand |
On 22/08/2022 16:03, Shubhrajyoti Datta wrote: > From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > > Some of the implementations support only 32-bit accesses. > Add a parameter reg-io-width for such platforms. > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > --- > v3: > patch addition > > Documentation/devicetree/bindings/serial/pl011.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml > index d8aed84abcd3..c8a4cbb178fe 100644 > --- a/Documentation/devicetree/bindings/serial/pl011.yaml > +++ b/Documentation/devicetree/bindings/serial/pl011.yaml > @@ -94,6 +94,13 @@ properties: > resets: > maxItems: 1 > > + reg-io-width: > + description: | No need for | > + The size (in bytes) of the IO accesses that should be performed > + on the device. > + $ref: /schemas/types.yaml#/definitions/uint32 This is a standard type, so no need for $ref Best regards, Krzysztof
From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> -Support uart peripheral in Xilinx Versal SOC. Add parameter reg-io-width. Add the dt-binding for the same v2: Update the commit message to reflect the AXI limitation. v3: Add reg-io-width. Shubhrajyoti Datta (2): dt-bindings: serial: pl011: Add a reg-io-width parameter serial: pl011: Add reg-io-width parameters .../devicetree/bindings/serial/pl011.yaml | 7 +++++++ drivers/tty/serial/amba-pl011.c | 16 ++++++++++++++++ 2 files changed, 23 insertions(+)