| Message ID | 20220817095629.29911-1-moudy.ho@mediatek.com |
|---|---|
| Headers | show |
| Series | media: mediatek: support mdp3 on mt8183 platform | expand |
On 17/08/2022 11:56, Moudy Ho wrote: > This patch adds DT binding documentation for MediaTek's CCORR and > WDMA components. > These components exist in both MediaTek's Media Data Path 3(MDP3) and DRM, > and the bindings are placed under the folder "./soc/mediatek" to prevent > duplicate builds. > > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> > Reviewed-by: Rob Herring <robh@kernel.org> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > .../bindings/soc/mediatek/mediatek,ccorr.yaml | 68 ++++++++++++++++ > .../bindings/soc/mediatek/mediatek,wdma.yaml | 81 +++++++++++++++++++ > 2 files changed, 149 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml > create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml > new file mode 100644 > index 000000000000..10786d769750 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml > @@ -0,0 +1,68 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek color correction > + > +maintainers: > + - Matthias Brugger <matthias.bgg@gmail.com> > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com> Same here. Regards, Matthias > + > +description: | > + MediaTek color correction with 3X3 matrix. > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt8183-mdp3-ccorr > + > + reg: > + maxItems: 1 > + > + mediatek,gce-client-reg: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + items: > + - description: phandle of GCE > + - description: GCE subsys id > + - description: register offset > + - description: register size > + description: The register of client driver can be configured by gce with > + 4 arguments defined in this property. Each GCE subsys id is mapping to > + a client defined in the header include/dt-bindings/gce/<chip>-gce.h. > + > + mediatek,gce-events: > + description: > + The event id which is mapping to the specific hardware event signal > + to gce. The event id is defined in the gce header > + include/dt-bindings/gce/<chip>-gce.h of each chips. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + > + clocks: > + minItems: 1 > + > +required: > + - compatible > + - reg > + - mediatek,gce-client-reg > + - mediatek,gce-events > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mt8183-clk.h> > + #include <dt-bindings/gce/mt8183-gce.h> > + > + mdp3_ccorr: mdp3-ccorr@1401c000 { > + compatible = "mediatek,mt8183-mdp3-ccorr"; > + reg = <0x1401c000 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; > + mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>, > + <CMDQ_EVENT_MDP_CCORR_EOF>; > + clocks = <&mmsys CLK_MM_MDP_CCORR>; > + }; > diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > new file mode 100644 > index 000000000000..95ec19543945 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > @@ -0,0 +1,81 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Write Direct Memory Access > + > +maintainers: > + - Matthias Brugger <matthias.bgg@gmail.com> > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com> > + > +description: | > + MediaTek Write Direct Memory Access(WDMA) component used to write > + the data into DMA. > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt8183-mdp3-wdma > + > + reg: > + maxItems: 1 > + > + mediatek,gce-client-reg: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + items: > + - description: phandle of GCE > + - description: GCE subsys id > + - description: register offset > + - description: register size > + description: The register of client driver can be configured by gce with > + 4 arguments defined in this property. Each GCE subsys id is mapping to > + a client defined in the header include/dt-bindings/gce/<chip>-gce.h. > + > + mediatek,gce-events: > + description: > + The event id which is mapping to the specific hardware event signal > + to gce. The event id is defined in the gce header > + include/dt-bindings/gce/<chip>-gce.h of each chips. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + > + power-domains: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + > + iommus: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - mediatek,gce-client-reg > + - mediatek,gce-events > + - power-domains > + - clocks > + - iommus > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mt8183-clk.h> > + #include <dt-bindings/gce/mt8183-gce.h> > + #include <dt-bindings/power/mt8183-power.h> > + #include <dt-bindings/memory/mt8183-larb-port.h> > + > + mdp3_wdma: mdp3-wdma@14006000 { > + compatible = "mediatek,mt8183-mdp3-wdma"; > + reg = <0x14006000 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; > + mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>, > + <CMDQ_EVENT_MDP_WDMA0_EOF>; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_MDP_WDMA0>; > + iommus = <&iommu>; > + };
Hi Matthias, On Mon, 2022-08-22 at 16:31 +0200, Matthias Brugger wrote: > > On 17/08/2022 11:56, Moudy Ho wrote: > > This patch adds DT binding documents for Media Data Path 3 (MDP3) > > a unit in multimedia system combined with several components and > > used for scaling and color format convert. > > > > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> > > Reviewed-by: Rob Herring <robh@kernel.org> > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > --- > > .../bindings/media/mediatek,mdp3-rdma.yaml | 95 > > +++++++++++++++++++ > > .../bindings/media/mediatek,mdp3-rsz.yaml | 77 > > +++++++++++++++ > > .../bindings/media/mediatek,mdp3-wrot.yaml | 80 > > ++++++++++++++++ > > 3 files changed, 252 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml > > create mode 100644 > > Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml > > create mode 100644 > > Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml > > > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3- > > rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3- > > rdma.yaml > > new file mode 100644 > > index 000000000000..94ff74d9c04a > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3- > > rdma.yaml > > @@ -0,0 +1,95 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!yGA_w2I4HGhwI-nLMb62fFdTf--h1GdolE2RQhH3DW1AWh0WR0AX4klb8Q2Znasv$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!yGA_w2I4HGhwI-nLMb62fFdTf--h1GdolE2RQhH3DW1AWh0WR0AX4klb8RCccQrB$ > > > > + > > +title: MediaTek Read Direct Memory Access > > + > > +maintainers: > > + - Matthias Brugger <matthias.bgg@gmail.com> > > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com> > > Ping-Hsun Wu isn't even CCed on this mail. Why aren't you the > maintainer if you > submit the patch? > > Regards, > Matthias > Thank you for your attention to this matter and apologies for the wrong candidate. I'll relist the correct maintainers and release a new version for it. Regards, Moudy > > + > > +description: | > > + MediaTek Read Direct Memory Access(RDMA) component used to do > > read DMA. > > + It contains one line buffer to store the sufficient pixel data, > > and > > + must be siblings to the central MMSYS_CONFIG node. > > + For a description of the MMSYS_CONFIG binding, see > > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.ya > > ml > > + for details. > > + > > +properties: > > + compatible: > > + items: > > + - const: mediatek,mt8183-mdp3-rdma > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,gce-client-reg: > > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > > + items: > > + items: > > + - description: phandle of GCE > > + - description: GCE subsys id > > + - description: register offset > > + - description: register size > > + description: The register of client driver can be configured > > by gce with > > + 4 arguments defined in this property. Each GCE subsys id is > > mapping to > > + a client defined in the header include/dt- > > bindings/gce/<chip>-gce.h. > > + > > + mediatek,gce-events: > > + description: > > + The event id which is mapping to the specific hardware event > > signal > > + to gce. The event id is defined in the gce header > > + include/dt-bindings/gce/<chip>-gce.h of each chips. > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: RDMA clock > > + - description: RSZ clock > > + > > + iommus: > > + maxItems: 1 > > + > > + mboxes: > > + items: > > + - description: used for 1st data pipe from RDMA > > + - description: used for 2nd data pipe from RDMA > > + > > +required: > > + - compatible > > + - reg > > + - mediatek,gce-client-reg > > + - mediatek,gce-events > > + - power-domains > > + - clocks > > + - iommus > > + - mboxes > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt8183-clk.h> > > + #include <dt-bindings/gce/mt8183-gce.h> > > + #include <dt-bindings/power/mt8183-power.h> > > + #include <dt-bindings/memory/mt8183-larb-port.h> > > + > > + mdp3_rdma0: mdp3-rdma0@14001000 { > > + compatible = "mediatek,mt8183-mdp3-rdma"; > > + reg = <0x14001000 0x1000>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 > > 0x1000>; > > + mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, > > + <CMDQ_EVENT_MDP_RDMA0_EOF>; > > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_MDP_RDMA0>, > > + <&mmsys CLK_MM_MDP_RSZ1>; > > + iommus = <&iommu>; > > + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, > > + <&gce 21 CMDQ_THR_PRIO_LOWEST>; > > + }; > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3- > > rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3- > > rsz.yaml > > new file mode 100644 > > index 000000000000..22c61ed00fdd > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3- > > rsz.yaml > > @@ -0,0 +1,77 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml*__;Iw!!CTRNKA9wMg0ARbw!yGA_w2I4HGhwI-nLMb62fFdTf--h1GdolE2RQhH3DW1AWh0WR0AX4klb8XW2iViE$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!yGA_w2I4HGhwI-nLMb62fFdTf--h1GdolE2RQhH3DW1AWh0WR0AX4klb8RCccQrB$ > > > > + > > +title: MediaTek Resizer > > + > > +maintainers: > > + - Matthias Brugger <matthias.bgg@gmail.com> > > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com> > > + > > +description: | > > + One of Media Data Path 3 (MDP3) components used to do frame > > resizing. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt8183-mdp3-rsz > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,gce-client-reg: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + items: > > + - description: phandle of GCE > > + - description: GCE subsys id > > + - description: register offset > > + - description: register size > > + description: The register of client driver can be configured > > by gce with > > + 4 arguments defined in this property. Each GCE subsys id is > > mapping to > > + a client defined in the header include/dt- > > bindings/gce/<chip>-gce.h. > > + > > + mediatek,gce-events: > > + description: > > + The event id which is mapping to the specific hardware event > > signal > > + to gce. The event id is defined in the gce header > > + include/dt-bindings/gce/<chip>-gce.h of each chips. > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + > > + clocks: > > + minItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - mediatek,gce-client-reg > > + - mediatek,gce-events > > + - clocks > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt8183-clk.h> > > + #include <dt-bindings/gce/mt8183-gce.h> > > + > > + mdp3_rsz0: mdp3-rsz0@14003000 { > > + compatible = "mediatek,mt8183-mdp3-rsz"; > > + reg = <0x14003000 0x1000>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 > > 0x1000>; > > + mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>, > > + <CMDQ_EVENT_MDP_RSZ0_EOF>; > > + clocks = <&mmsys CLK_MM_MDP_RSZ0>; > > + }; > > + > > + mdp3_rsz1: mdp3-rsz1@14004000 { > > + compatible = "mediatek,mt8183-mdp3-rsz"; > > + reg = <0x14004000 0x1000>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 > > 0x1000>; > > + mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>, > > + <CMDQ_EVENT_MDP_RSZ1_EOF>; > > + clocks = <&mmsys CLK_MM_MDP_RSZ1>; > > + }; > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3- > > wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3- > > wrot.yaml > > new file mode 100644 > > index 000000000000..76c010720d43 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3- > > wrot.yaml > > @@ -0,0 +1,80 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml*__;Iw!!CTRNKA9wMg0ARbw!yGA_w2I4HGhwI-nLMb62fFdTf--h1GdolE2RQhH3DW1AWh0WR0AX4klb8Til05HT$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!yGA_w2I4HGhwI-nLMb62fFdTf--h1GdolE2RQhH3DW1AWh0WR0AX4klb8RCccQrB$ > > > > + > > +title: MediaTek Write DMA with Rotation > > + > > +maintainers: > > + - Matthias Brugger <matthias.bgg@gmail.com> > > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com> > > + > > +description: | > > + One of Media Data Path 3 (MDP3) components used to write DMA > > with frame rotation. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt8183-mdp3-wrot > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,gce-client-reg: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + items: > > + - description: phandle of GCE > > + - description: GCE subsys id > > + - description: register offset > > + - description: register size > > + description: The register of client driver can be configured > > by gce with > > + 4 arguments defined in this property. Each GCE subsys id is > > mapping to > > + a client defined in the header include/dt- > > bindings/gce/<chip>-gce.h. > > + > > + mediatek,gce-events: > > + description: > > + The event id which is mapping to the specific hardware event > > signal > > + to gce. The event id is defined in the gce header > > + include/dt-bindings/gce/<chip>-gce.h of each chips. > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + minItems: 1 > > + > > + iommus: > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - mediatek,gce-client-reg > > + - mediatek,gce-events > > + - power-domains > > + - clocks > > + - iommus > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt8183-clk.h> > > + #include <dt-bindings/gce/mt8183-gce.h> > > + #include <dt-bindings/power/mt8183-power.h> > > + #include <dt-bindings/memory/mt8183-larb-port.h> > > + > > + mdp3_wrot0: mdp3-wrot0@14005000 { > > + compatible = "mediatek,mt8183-mdp3-wrot"; > > + reg = <0x14005000 0x1000>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 > > 0x1000>; > > + mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>, > > + <CMDQ_EVENT_MDP_WROT0_EOF>; > > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_MDP_WROT0>; > > + iommus = <&iommu>; > > + };
Hi Matthias, On Mon, 2022-08-22 at 16:32 +0200, Matthias Brugger wrote: > > On 17/08/2022 11:56, Moudy Ho wrote: > > This patch adds DT binding documentation for MediaTek's CCORR and > > WDMA components. > > These components exist in both MediaTek's Media Data Path 3(MDP3) > > and DRM, > > and the bindings are placed under the folder "./soc/mediatek" to > > prevent > > duplicate builds. > > > > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> > > Reviewed-by: Rob Herring <robh@kernel.org> > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > --- > > .../bindings/soc/mediatek/mediatek,ccorr.yaml | 68 > > ++++++++++++++++ > > .../bindings/soc/mediatek/mediatek,wdma.yaml | 81 > > +++++++++++++++++++ > > 2 files changed, 149 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml > > create mode 100644 > > Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam > > l > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam > > l > > new file mode 100644 > > index 000000000000..10786d769750 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam > > l > > @@ -0,0 +1,68 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml*__;Iw!!CTRNKA9wMg0ARbw!3h7qYnjiwvN90iwxMZCIpxo-QWZqllWu4mMpB6NSjDHPKnuM4mITblmweAeVniXJ$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!3h7qYnjiwvN90iwxMZCIpxo-QWZqllWu4mMpB6NSjDHPKnuM4mITblmweCOWt0j9$ > > > > + > > +title: MediaTek color correction > > + > > +maintainers: > > + - Matthias Brugger <matthias.bgg@gmail.com> > > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com> > > Same here. > > Regards, > Matthias > Thanks for the reminder, I'll deal with it together with the previous patch Regards, Moudy > > + > > +description: | > > + MediaTek color correction with 3X3 matrix. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt8183-mdp3-ccorr > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,gce-client-reg: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + items: > > + - description: phandle of GCE > > + - description: GCE subsys id > > + - description: register offset > > + - description: register size > > + description: The register of client driver can be configured > > by gce with > > + 4 arguments defined in this property. Each GCE subsys id is > > mapping to > > + a client defined in the header include/dt- > > bindings/gce/<chip>-gce.h. > > + > > + mediatek,gce-events: > > + description: > > + The event id which is mapping to the specific hardware event > > signal > > + to gce. The event id is defined in the gce header > > + include/dt-bindings/gce/<chip>-gce.h of each chips. > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + > > + clocks: > > + minItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - mediatek,gce-client-reg > > + - mediatek,gce-events > > + - clocks > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt8183-clk.h> > > + #include <dt-bindings/gce/mt8183-gce.h> > > + > > + mdp3_ccorr: mdp3-ccorr@1401c000 { > > + compatible = "mediatek,mt8183-mdp3-ccorr"; > > + reg = <0x1401c000 0x1000>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 > > 0x1000>; > > + mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>, > > + <CMDQ_EVENT_MDP_CCORR_EOF>; > > + clocks = <&mmsys CLK_MM_MDP_CCORR>; > > + }; > > diff --git > > a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > new file mode 100644 > > index 000000000000..95ec19543945 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > @@ -0,0 +1,81 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!3h7qYnjiwvN90iwxMZCIpxo-QWZqllWu4mMpB6NSjDHPKnuM4mITblmweNEpTeKs$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!3h7qYnjiwvN90iwxMZCIpxo-QWZqllWu4mMpB6NSjDHPKnuM4mITblmweCOWt0j9$ > > > > + > > +title: MediaTek Write Direct Memory Access > > + > > +maintainers: > > + - Matthias Brugger <matthias.bgg@gmail.com> > > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com> > > + > > +description: | > > + MediaTek Write Direct Memory Access(WDMA) component used to > > write > > + the data into DMA. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt8183-mdp3-wdma > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,gce-client-reg: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + items: > > + - description: phandle of GCE > > + - description: GCE subsys id > > + - description: register offset > > + - description: register size > > + description: The register of client driver can be configured > > by gce with > > + 4 arguments defined in this property. Each GCE subsys id is > > mapping to > > + a client defined in the header include/dt- > > bindings/gce/<chip>-gce.h. > > + > > + mediatek,gce-events: > > + description: > > + The event id which is mapping to the specific hardware event > > signal > > + to gce. The event id is defined in the gce header > > + include/dt-bindings/gce/<chip>-gce.h of each chips. > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + minItems: 1 > > + > > + iommus: > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - mediatek,gce-client-reg > > + - mediatek,gce-events > > + - power-domains > > + - clocks > > + - iommus > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt8183-clk.h> > > + #include <dt-bindings/gce/mt8183-gce.h> > > + #include <dt-bindings/power/mt8183-power.h> > > + #include <dt-bindings/memory/mt8183-larb-port.h> > > + > > + mdp3_wdma: mdp3-wdma@14006000 { > > + compatible = "mediatek,mt8183-mdp3-wdma"; > > + reg = <0x14006000 0x1000>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 > > 0x1000>; > > + mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>, > > + <CMDQ_EVENT_MDP_WDMA0_EOF>; > > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_MDP_WDMA0>; > > + iommus = <&iommu>; > > + };
Change since v24: - Rebase on v6.0-rc1. Change since v23: - Rebase on linux-next. - Fix compilation error. Change since v22: - Rebase on linux-next. - Fix typo about MDP3 in Kconfig. - Adjust some non-essential logs to lower levels. Change since v21: - Rebase on linux-next. - Following Hans suggestion, remove redundant kernel logs and revise a few non-functional code to make it clearer. - Remove API abuse to set plane size. - Added VPU send message failure error code for previous shortages. Change since v20: - Rebase on linux-next. - Move the MDP3 GCE events to the corresponding node and adjust the relevant driver settings. Change since v19: - Rebase on linux-next. - Export the function "mdp_cmdq_send" suggected by CK. - Fix "Macro argument reuse" reported by checkpatch.pl Change since v18: - Rebase on linux-next. - Adjust copyright date of MDP3 driver. - Functions renaming as follows: [1] is_output_disable() => is_output_disabled() [2] mdp_component_init() => mdp_comp_config() [3] mdp_component_deinit() => mdp_comp_destroy() [4] mdp_comp_ctx_init() => mdp_comp_ctx_config() [5] mdp_sub_comps_create() => mdp_comp_sub_create() - Document MDP3 10-bit format descriptions in "mtk-mdp3-regs.c". - Add error control for functions mdp_comp_clocks_on and mdp_comp_clock_on. - Moved function "mtk_mutex_put" from function "mdp_comp_destroy"(renamed from mdp_component_deinit) to avoid semantic ambiguity. - For some allocated parameters, assign a value of NULL after freeing to avoid the possibility of repeated use. - Removed unnecessary timestamp pass flow. - About parameters passed by the user in function "mdp_try_fmt_mplane", add relevant checks to clamp them in a reasonable range to avoid the possibility of overflow Change since v17: - Depend on: [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=649104 - In response to future CMDQ api changes listed below: https://patchwork.kernel.org/project/linux-mediatek/patch/20220608144055.27562-1-chunkuang.hu@kernel.org/ adjust CMDQ flush and callback flow in MDP3. Change since v16: - Rebased on v5.19-rc1 - Depend on: [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=646131 - In response to MUTEX changes, adjust API naming and parameters when used in function "mdp_path_subfrm_require". - Remove unnecessary MDP3 phandle in 8183 dts. Change since v15: - Depend on: [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=640926 - Split the bindings under ./soc/mediatek into a separate patch. - Fix data abort in "mdp_auto_release_work" - Adjust the steps in the function "mdp_cmdq_send" to make the error handling more reasonable Change since v14: - Rebase on v5.18-rc6 - Depend on: [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=640926 - In response to CMDQ API change, replace the function "cmdq_pkt_flush_async" with the standard APIs of mbox - Fix the description of "mediatek,gce-client-reg" property in MDP3-related bindings Change since v13: - Rebase on v5.18-rc4 - Depend on: [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=636041 - Remove advanced functionality about ISP settings for direct link cases. - Remove the software designation in the mt8183 dts and revise corresponding bindings. Change since v12: - Rebase on linux-next - Depend on: [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=630948 - Remove messages related to routing information in MDP3, and leave the related settings in MMSYS. - Remove unnecessary phandle and redundant property in RDMA dt-binding and adjust the corresponding driver. - Revise MDP3 node name in dts. - Removed unnecessary functions, mutex and work queue in MDP3 driver - Fixed format mapping error for V4L2_PIX_FMT_RGB565X Change since v11: - Rebase on linux-next tag:next-20220316 - Depend on: [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=624281 - Remove redundant hardware index in data-binding suggested by Rob Herring. - Referring to Rob Herring's suggestion to improve some descriptions in the RDMA dt-binding - Move MDP3 file folder from "./drive/media/platform/mtk-mdp3" to "./driver/media/platform/mediatek/mdp3" - Fixed the V4L2 and MDP color format mapping error in RGB565 which checked by Benjamin Gaignard Change since v10: - The routing table needs to be discarded, and the calculation result on the SCP side is used to write a suitable mux setting for 1 input port and 2 output ports. - Adjust dts parsing flow to remove redundant HW IDs. - Fix memory leak caused by no free path information in function "mdp_cmdq_send". Change since v9: - Keep only the MDP3 driver patches and split the remaining mmsys and mutex patches into another mail. - Move mutex mod settings to corresponding driver and make relevant adjustments for this in MDP3 driver. - Fix compile warning reported by kernel test robot. Change since v8: - Rebase on v5.16-rc2. - Refer to Angelo's suggestion, adjust the register writing format to increase readability and significance. - Refer to Angelo's suggestion, adjust or reduce inappropriate debugging messages. - Refer to Rob Herring's suggestion to correct the the binding file to make it with the specification. - Fix compile warning reported by kernel test robot. Change since v7: - Rebase on v5.15-rc6. - Revise several V4L2 M2M settings to pass v4l2-compliance test. - Integrate those same component dt-binding documents of DRM and MDP, and move them under the MMSYS domain. - Split MMSYS and MUTEX into two different files according to their functional properties. Changes since v6: - Refactor GCE event to corresponding node. - Fix dt_binding_check fail. - Fix compilation errors. Changes since v5: - Rebase on v5.14-rc6. - Move MMSYS/Mutex settings to corresponding driver. - Revise the software license description and copyright. - Remove unnecessary enum. or definitions. - Optimize platform/chip definition conditions. - Use general printing functions instead of MDP3 private ones. - Fix compile warning. Changes since v4: - Rebase on v5.13-rc1. - Remove the CMDQ flush flow to match the CMDQ API change. - Integrate four of MDP's direct-link subcomponents into MDP controller node from syscon node to avoid illegal clock usage. - Rewrite dt-binding in a JSON compatible subset of YAML - Fix a bit of macro argument precedence. Changes since v3: - Rebase on v5.9-rc1. - modify code for review comment from Rob Herring, cancel multiple nodes using same register base situation. - control IOMMU port through pm runtime get/put to DMA components' device. - SCP(VPU) driver revision. - stop queuing jobs(remove flush_workqueue()) after mdp_m2m_release(). - add computation of plane address with data_offset. - fix scale ratio check issue. - add default v4l2_format setting. Changes since v2: - modify code for review comment from Tomasz Figa & Alexandre Courbot - review comment from Rob Herring will offer code revision in v4, due to it's related to device node modification, will need to modify code architecture Changes since v1: - modify code for CMDQ v3 API support - EC ipi cmd migration - fix compliance test fail item (m2m cmd with -f) due to there is two problem in runing all format(-f) cmd: 1. out of memory before test complete Due to capture buffer mmap (refcount + 1) after reqbuf but seems no corresponding munmap called before device close. There are total 12XX items(formats) in format test and each format alloc 8 capture/output buffers. 2. unceasingly captureBufs() (randomly) Seems the break statement didn't catch the count == 0 situation: In v4l2-test-buffers.cpp, function: captureBufs() ... count--; if (!node->is_m2m && !count) break; Log is as attachment Hi, This patch is used to present Media Data Path 3 (MDP3) which provided scaling and color format conversion. support using GCE to write register in critical time limitation. support V4L2 m2m device control. Moudy Ho (4): dt-binding: mediatek: add bindings for MediaTek MDP3 components dt-binding: mediatek: add bindings for MediaTek CCORR and WDMA arm64: dts: mt8183: add MediaTek MDP3 nodes media: platform: mtk-mdp3: add MediaTek MDP3 driver .../bindings/media/mediatek,mdp3-rdma.yaml | 95 ++ .../bindings/media/mediatek,mdp3-rsz.yaml | 77 ++ .../bindings/media/mediatek,mdp3-wrot.yaml | 80 ++ .../bindings/soc/mediatek/mediatek,ccorr.yaml | 68 ++ .../bindings/soc/mediatek/mediatek,wdma.yaml | 81 ++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 63 + drivers/media/platform/mediatek/Kconfig | 1 + drivers/media/platform/mediatek/Makefile | 1 + drivers/media/platform/mediatek/mdp3/Kconfig | 20 + drivers/media/platform/mediatek/mdp3/Makefile | 6 + .../platform/mediatek/mdp3/mdp_reg_ccorr.h | 19 + .../platform/mediatek/mdp3/mdp_reg_rdma.h | 65 ++ .../platform/mediatek/mdp3/mdp_reg_rsz.h | 39 + .../platform/mediatek/mdp3/mdp_reg_wdma.h | 47 + .../platform/mediatek/mdp3/mdp_reg_wrot.h | 55 + .../platform/mediatek/mdp3/mtk-img-ipi.h | 290 +++++ .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 466 ++++++++ .../platform/mediatek/mdp3/mtk-mdp3-cmdq.h | 43 + .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 1031 +++++++++++++++++ .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 186 +++ .../platform/mediatek/mdp3/mtk-mdp3-core.c | 357 ++++++ .../platform/mediatek/mdp3/mtk-mdp3-core.h | 94 ++ .../platform/mediatek/mdp3/mtk-mdp3-m2m.c | 724 ++++++++++++ .../platform/mediatek/mdp3/mtk-mdp3-m2m.h | 48 + .../platform/mediatek/mdp3/mtk-mdp3-regs.c | 733 ++++++++++++ .../platform/mediatek/mdp3/mtk-mdp3-regs.h | 373 ++++++ .../platform/mediatek/mdp3/mtk-mdp3-vpu.c | 313 +++++ .../platform/mediatek/mdp3/mtk-mdp3-vpu.h | 78 ++ 28 files changed, 5453 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml create mode 100644 drivers/media/platform/mediatek/mdp3/Kconfig create mode 100644 drivers/media/platform/mediatek/mdp3/Makefile create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_ccorr.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_wdma.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.h create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.h create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.h create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.h