| Message ID | 20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| Headers | show |
| Series | Add support for Renesas RZ/Five SoC | expand |
On 15/08/2022 18:14, Lad Prabhakar wrote: > Document Renesas RZ/Five (R9A07G043) SoC. > > More info about RZ/Five SoC: > https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
Hi Conor, On Fri, Aug 19, 2022 at 8:40 PM <Conor.Dooley@microchip.com> wrote: > On 15/08/2022 16:14, Lad Prabhakar wrote: > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > > Single). > > > > Below is the list of IP blocks added in the initial SoC DTSI which can be > > used to boot via initramfs on RZ/Five SMARC EVK: > > - AX45MP CPU > > - CPG > > - PINCTRL > > - PLIC > > - SCIF0 > > - SYSC > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > v1->v2 > > * Dropped including makefile change > > * Updated ndev count > > --- > > arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++ > > 1 file changed, 121 insertions(+) > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi > > new file mode 100644 > > index 000000000000..b288d2607796 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi > > @@ -0,0 +1,121 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +/* > > + * Device Tree Source for the RZ/Five SoC > > + * > > + * Copyright (C) 2022 Renesas Electronics Corp. > > + */ > > + > > +#include <dt-bindings/interrupt-controller/irq.h> > > +#include <dt-bindings/clock/r9a07g043-cpg.h> > > + > > +/ { > > + compatible = "renesas,r9a07g043"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ > > + extal_clk: extal-clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + /* This value must be overridden by the board */ > > + clock-frequency = <0>; > > What's the value in having the clock-frequency here if the board .dtsi > overwrites it? dtbs_check will complain if someone forgets to fill it > IIUC & what the missing frequency means is also kinda obvious, no? Some external clocks may be optional. Hence "dtbs_check" will complain if no "clock-frequency" is missing. > > That aside, by convention so far we have put things like extals or > reference clocks below the /cpus node. Could you do the same here too > please? Really? We've been putting them at the root node for a long time, since the separate "clocks" grouping subnode was deprecated. The extal-clk is not even part of the SoC, so it should definitely not be under the /cpus node. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On 20/08/2022 09:45, Geert Uytterhoeven wrote: > Hi Conor, > > On Fri, Aug 19, 2022 at 8:40 PM <Conor.Dooley@microchip.com> wrote: >> On 15/08/2022 16:14, Lad Prabhakar wrote: >>> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP >>> Single). >>> >>> Below is the list of IP blocks added in the initial SoC DTSI which can be >>> used to boot via initramfs on RZ/Five SMARC EVK: >>> - AX45MP CPU >>> - CPG >>> - PINCTRL >>> - PLIC >>> - SCIF0 >>> - SYSC >>> >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> >>> --- >>> v1->v2 >>> * Dropped including makefile change >>> * Updated ndev count >>> --- >>> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++ >>> 1 file changed, 121 insertions(+) >>> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi >>> >>> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi >>> new file mode 100644 >>> index 000000000000..b288d2607796 >>> --- /dev/null >>> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi >>> @@ -0,0 +1,121 @@ >>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +/* >>> + * Device Tree Source for the RZ/Five SoC >>> + * >>> + * Copyright (C) 2022 Renesas Electronics Corp. >>> + */ >>> + >>> +#include <dt-bindings/interrupt-controller/irq.h> >>> +#include <dt-bindings/clock/r9a07g043-cpg.h> >>> + >>> +/ { >>> + compatible = "renesas,r9a07g043"; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + >>> + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ >>> + extal_clk: extal-clk { >>> + compatible = "fixed-clock"; >>> + #clock-cells = <0>; >>> + /* This value must be overridden by the board */ >>> + clock-frequency = <0>; >> >> What's the value in having the clock-frequency here if the board .dtsi >> overwrites it? dtbs_check will complain if someone forgets to fill it >> IIUC & what the missing frequency means is also kinda obvious, no? > > Some external clocks may be optional. Hence "dtbs_check" will complain > if no "clock-frequency" is missing. Right, seems reasonable enough. > >> >> That aside, by convention so far we have put things like extals or >> reference clocks below the /cpus node. Could you do the same here too >> please? > > Really? We've been putting them at the root node for a long time, > since the separate "clocks" grouping subnode was deprecated. > The extal-clk is not even part of the SoC, so it should definitely > not be under the /cpus node. Under may have been a confusing choice of words, I meant "physically" under it in the file. Maybe after would have been a better choice of words? I wasn't suggesting you put it inside the CPUs node. Does that make more sense? Conor.
Hi Conor, On Sat, Aug 20, 2022 at 10:49 AM <Conor.Dooley@microchip.com> wrote: > On 20/08/2022 09:45, Geert Uytterhoeven wrote: > > On Fri, Aug 19, 2022 at 8:40 PM <Conor.Dooley@microchip.com> wrote: > >> On 15/08/2022 16:14, Lad Prabhakar wrote: > >>> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > >>> Single). > >>> > >>> Below is the list of IP blocks added in the initial SoC DTSI which can be > >>> used to boot via initramfs on RZ/Five SMARC EVK: > >>> - AX45MP CPU > >>> - CPG > >>> - PINCTRL > >>> - PLIC > >>> - SCIF0 > >>> - SYSC > >>> > >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > >> That aside, by convention so far we have put things like extals or > >> reference clocks below the /cpus node. Could you do the same here too > >> please? > > > > Really? We've been putting them at the root node for a long time, > > since the separate "clocks" grouping subnode was deprecated. > > The extal-clk is not even part of the SoC, so it should definitely > > not be under the /cpus node. > > Under may have been a confusing choice of words, I meant "physically" > under it in the file. Maybe after would have been a better choice of > words? I wasn't suggesting you put it inside the CPUs node. > Does that make more sense? Oh right, you mean the order of the nodes. Yes, "extal-clk" should be after "cpus", following alphabetical sort order, as the nodes have no unit addresses. Sorry for missing that in my review. I also misread "below" (in Dutch there is only a single word for "below" and "under" ;-) Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi All, The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as entry-class social infrastructure gateway control and industrial gateway control. This patch series adds initial SoC DTSi support for Renesas RZ/Five (R9A07G043) SoC and updates the bindings for the same. Below is the list of IP blocks added in the initial SoC DTSI which can be used to boot via initramfs on RZ/Five SMARC EVK: - AX45MP CPU - CPG - PINCTRL - PLIC - SCIF0 - SYSC Useful links: ------------- [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet [1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/ Patch series depends on: ----------------------- [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20220722141506.20171-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220726174525.620-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ [2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220726174929.950-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ [3] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220726175315.1147-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ [4] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220815111708.22302-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Below are the logs from RZ/Five SMARC EVK: ------------------------------------------ / # uname -ra Linux (none) 5.19.0-next-20220815-00072-ge2dccecbe54f #256 SMP Mon Aug 15 15:12:03 BST 2022 riscv64 GNU/Linux / # / # cat /proc/cpuinfo processor : 0 hart : 0 isa : rv64imafdc mmu : sv39 uarch : andestech,ax45mp mvendorid : 0x31e marchid : 0x8000000000008a45 mimpid : 0x500 / # cat /proc/interrupts CPU0 1: 0 SiFive PLIC 412 Level 1004b800.serial:rx err 2: 1 SiFive PLIC 414 Level 1004b800.serial:rx full 3: 181 SiFive PLIC 415 Level 1004b800.serial:tx empty 4: 0 SiFive PLIC 413 Level 1004b800.serial:break 5: 2435 RISC-V INTC 5 Edge riscv-timer 6: 38 SiFive PLIC 416 Level 1004b800.serial:rx ready IPI0: 0 Rescheduling interrupts IPI1: 0 Function call interrupts IPI2: 0 CPU stop interrupts IPI3: 0 IRQ work interrupts IPI4: 0 Timer broadcast interrupts / # cat /proc/meminfo MemTotal: 882356 kB MemFree: 861996 kB MemAvailable: 859744 kB Buffers: 0 kB Cached: 1796 kB SwapCached: 0 kB Active: 0 kB Inactive: 80 kB Active(anon): 0 kB Inactive(anon): 80 kB Active(file): 0 kB Inactive(file): 0 kB Unevictable: 1796 kB Mlocked: 0 kB SwapTotal: 0 kB SwapFree: 0 kB Dirty: 0 kB Writeback: 0 kB AnonPages: 116 kB Mapped: 1136 kB Shmem: 0 kB KReclaimable: 6732 kB Slab: 11904 kB SReclaimable: 6732 kB SUnreclaim: 5172 kB KernelStack: 556 kB PageTables: 32 kB NFS_Unstable: 0 kB Bounce: 0 kB WritebackTmp: 0 kB CommitLimit: 441176 kB Committed_AS: 592 kB VmallocTotal: 67108864 kB VmallocUsed: 716 kB VmallocChunk: 0 kB Percpu: 84 kB HugePages_Total: 0 HugePages_Free: 0 HugePages_Rsvd: 0 HugePages_Surp: 0 Hugepagesize: 2048 kB Hugetlb: 0 kB / # / # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/ soc0/$i; done machine: Renesas SMARC EVK based on r9a07g043f01 family: RZ/Five soc_id: r9a07g043 revision: 0 / # Lad Prabhakar (8): dt-bindings: riscv: Sort the CPU core list alphabetically dt-bindings: riscv: Add Andes AX45MP core to the list dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK MAINTAINERS: Add entry for Renesas RISC-V architecture RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC .../devicetree/bindings/arm/renesas.yaml | 3 +- .../devicetree/bindings/riscv/cpus.yaml | 11 +- MAINTAINERS | 10 ++ arch/riscv/Kconfig.socs | 14 ++ arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/renesas/Makefile | 2 + arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 ++++++++++++++++++ .../boot/dts/renesas/r9a07g043f01-smarc.dts | 16 +++ .../boot/dts/renesas/rzfive-smarc-som.dtsi | 22 ++++ arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++ arch/riscv/configs/defconfig | 2 + 11 files changed, 228 insertions(+), 6 deletions(-) create mode 100644 arch/riscv/boot/dts/renesas/Makefile create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi