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[v3,0/2] ufs: allow host driver disable wb toggle druing clock scaling

Message ID 20220802143223.1276-1-peter.wang@mediatek.com
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Series ufs: allow host driver disable wb toggle druing clock scaling | expand

Message

Peter Wang (王信友) Aug. 2, 2022, 2:32 p.m. UTC
From: Peter Wang <peter.wang@mediatek.com>

Mediatek ufs do not want to toggle write booster during clock scaling. 
This patch set allow host driver disable wb toggle during clock scaling.

Peter Wang (2):
  ufs: core: introduce a choice of wb toggle during clock scaling
  ufs: host: support wb toggle with clock scaling

 drivers/ufs/core/ufs-sysfs.c | 3 ++-
 drivers/ufs/core/ufshcd.c    | 8 +++++---
 drivers/ufs/host/ufs-qcom.c  | 2 +-
 include/ufs/ufshcd.h         | 7 +++++++
 4 files changed, 15 insertions(+), 5 deletions(-)

Comments

Bart Van Assche Aug. 2, 2022, 6:46 p.m. UTC | #1
On 8/2/22 07:32, peter.wang@mediatek.com wrote:
> From: Peter Wang <peter.wang@mediatek.com>
> 
> Set UFSHCD_CAP_WB_WITH_CLK_SCALING for qcom to compatible legacy design.
> 
> Signed-off-by: Peter Wang <peter.wang@mediatek.com>
> Reviewed-by: Stanley Chu <stanley.chu@mediatek.com>
> ---
>   drivers/ufs/host/ufs-qcom.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index f10d4668814c..f8c9a78e7776 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -869,7 +869,7 @@ static void ufs_qcom_set_caps(struct ufs_hba *hba)
>   	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
>   
>   	hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
> -	hba->caps |= UFSHCD_CAP_CLK_SCALING;
> +	hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING;
>   	hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
>   	hba->caps |= UFSHCD_CAP_WB_EN;
>   	hba->caps |= UFSHCD_CAP_CRYPTO;

A patch series should be bisectable. Without this patch the previous 
patch in this series introduces a regression for Qualcomm controllers. 
So I think that the two patches should be combined into a single patch.

Thanks,

Bart.
Peter Wang (王信友) Aug. 3, 2022, 2:42 a.m. UTC | #2
On 8/3/22 2:46 AM, Bart Van Assche wrote:
> On 8/2/22 07:32, peter.wang@mediatek.com wrote:
>> From: Peter Wang <peter.wang@mediatek.com>
>>
>> Set UFSHCD_CAP_WB_WITH_CLK_SCALING for qcom to compatible legacy design.
>>
>> Signed-off-by: Peter Wang <peter.wang@mediatek.com>
>> Reviewed-by: Stanley Chu <stanley.chu@mediatek.com>
>> ---
>>   drivers/ufs/host/ufs-qcom.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>> index f10d4668814c..f8c9a78e7776 100644
>> --- a/drivers/ufs/host/ufs-qcom.c
>> +++ b/drivers/ufs/host/ufs-qcom.c
>> @@ -869,7 +869,7 @@ static void ufs_qcom_set_caps(struct ufs_hba *hba)
>>       struct ufs_qcom_host *host = ufshcd_get_variant(hba);
>>         hba->caps |= UFSHCD_CAP_CLK_GATING | 
>> UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
>> -    hba->caps |= UFSHCD_CAP_CLK_SCALING;
>> +    hba->caps |= UFSHCD_CAP_CLK_SCALING | 
>> UFSHCD_CAP_WB_WITH_CLK_SCALING;
>>       hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
>>       hba->caps |= UFSHCD_CAP_WB_EN;
>>       hba->caps |= UFSHCD_CAP_CRYPTO;
>
> A patch series should be bisectable. Without this patch the previous 
> patch in this series introduces a regression for Qualcomm controllers. 
> So I think that the two patches should be combined into a single patch.
>
> Thanks,
>
> Bart.

Hi Bart,

Will combine into a single patch next version.

Thanks.
Peter