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[v8,00/16] Introduce Nuvoton Arbel NPCM8XX BMC SoC

Message ID 20220711123519.217219-1-tmaimon77@gmail.com
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Series Introduce Nuvoton Arbel NPCM8XX BMC SoC | expand

Message

Tomer Maimon July 11, 2022, 12:35 p.m. UTC
This patchset  adds initial support for the Nuvoton 
Arbel NPCM8XX Board Management controller (BMC) SoC family. 

The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC.
The NPCM8XX computing subsystem comprises a quadcore ARM 
Cortex A35 ARM-V8 architecture.

This patchset adds minimal architecture and drivers such as:
Clocksource, Clock, Reset, and WD.

Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.

This patchset was tested on the Arbel NPCM8XX evaluation board.

Changes since version 7:
 - NPCM8XX clock driver
	- The clock and reset registers using the same memory region, 
	  due to it the clock driver should claim the ioremap directly 
	  without checking the memory region.

Changes since version 6:
 - NPCM reset driver
	- Modify warning message.
 - dt-bindings: serial: 8250: Add npcm845 compatible string patch accepted, due
   to it the patch removed from the patchset.

Changes since version 5:
 - NPCM8XX clock driver
	- Remove refclk if devm_of_clk_add_hw_provider function failed.
 - NPCM8XX clock source driver
	- Remove NPCM8XX TIMER_OF_DECLARE support, using the same as NPCM7XX.

Changes since version 4:
 - NPCM8XX clock driver
	- Use the same quote in the dt-binding file.

Changes since version 3:
 - NPCM8XX clock driver
	- Rename NPCM8xx clock dt-binding header file.
	- Remove unused structures.
	- Improve Handling the clocks registration.
 - NPCM reset driver
	- Add ref phandle to dt-binding.

Changes since version 2:
 - Remove NPCM8xx WDT compatible patch.
 - Remove NPCM8xx UART compatible patch.
 - NPCM8XX clock driver
	- Add debug new line.
	- Add 25M fixed rate clock.
	- Remove unused clocks and clock name from dt-binding.
 - NPCM reset driver
	- Revert to npcm7xx dt-binding.
	- Skip dt binding quotes.
	- Adding DTS backward compatibility.
	- Remove NPCM8xx binding include file.
	- Warp commit message.
- NPCM8XX device tree:
	- Remove unused clock nodes (used in the clock driver)
	- Modify gcr and rst node names.

Changes since version 1:
 - NPCM8XX clock driver
	- Modify dt-binding.
	- Remove unsed definition and include.
	- Include alphabetically.
	- Use clock devm.
 - NPCM reset driver
	- Modify dt-binding.
	- Modify syscon name.
	- Add syscon support to NPCM7XX dts reset node.
	- use data structure.
 - NPCM8XX device tree:
	- Modify evb compatible name.
	- Add NPCM7xx compatible.
	- Remove disable nodes from the EVB DTS.

Tomer Maimon (16):
  dt-bindings: timer: npcm: Add npcm845 compatible string
  dt-bindings: watchdog: npcm: Add npcm845 compatible string
  dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
  clk: npcm8xx: add clock controller
  dt-bindings: reset: npcm: add GCR syscon property
  ARM: dts: nuvoton: add reset syscon property
  reset: npcm: using syscon instead of device data
  dt-bindings: reset: npcm: Add support for NPCM8XX
  reset: npcm: Add NPCM8XX support
  dt-bindings: arm: npcm: Add maintainer
  dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
  dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
  arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
  arm64: dts: nuvoton: Add initial NPCM8XX device tree
  arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
  arm64: defconfig: Add Nuvoton NPCM family support

 .../devicetree/bindings/arm/npcm/npcm.yaml    |   7 +
 .../bindings/arm/npcm/nuvoton,gcr.yaml        |   2 +
 .../bindings/clock/nuvoton,npcm845-clk.yaml   |  49 ++
 .../bindings/reset/nuvoton,npcm750-reset.yaml |  10 +-
 .../bindings/timer/nuvoton,npcm7xx-timer.yaml |   2 +
 .../bindings/watchdog/nuvoton,npcm-wdt.txt    |   3 +-
 MAINTAINERS                                   |   2 +
 arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi |   1 +
 arch/arm64/Kconfig.platforms                  |  11 +
 arch/arm64/boot/dts/Makefile                  |   1 +
 arch/arm64/boot/dts/nuvoton/Makefile          |   2 +
 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 170 +++++
 .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  |  30 +
 .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |  76 +++
 arch/arm64/configs/defconfig                  |   3 +
 drivers/clk/Kconfig                           |   6 +
 drivers/clk/Makefile                          |   1 +
 drivers/clk/clk-npcm8xx.c                     | 610 ++++++++++++++++++
 drivers/reset/reset-npcm.c                    | 207 +++++-
 .../dt-bindings/clock/nuvoton,npcm845-clk.h   |  49 ++
 20 files changed, 1206 insertions(+), 36 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
 create mode 100644 arch/arm64/boot/dts/nuvoton/Makefile
 create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
 create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
 create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
 create mode 100644 drivers/clk/clk-npcm8xx.c
 create mode 100644 include/dt-bindings/clock/nuvoton,npcm845-clk.h

Comments

Stephen Boyd July 23, 2022, 3:02 a.m. UTC | #1
Quoting Tomer Maimon (2022-07-19 03:04:43)
> On Mon, 18 Jul 2022 at 22:14, Stephen Boyd <sboyd@kernel.org> wrote:
> >
> >
> > So the clk and reset driver should be the same driver, or one driver
> > should register the other and use the auxiliary bus to express the
> > relationship. That way we know that the drivers are tightly coupled and
> > aren't going to stomp over each other.
> I think it is very problematic to use the same driver for the reset
> and the clocks also because The NPCM reset driver is an old driver
> that was used also to the older NPCM BMC SoC so it will be problematic
> to use the clock and reset driver in the same space.
> indeed the reset and clocks are using the same memory region but they
> are not using the same registers, is it not enough?
> Please be aware that the NPCM reset driver is checking that it is
> using the reset registers before calling I/O functions.

To put it simply, platform device drivers should use platform device
APIs. The platform device APIs hide the fact that the firmware is ACPI
or DT or nothing at all. The usage of of_address_to_resource() is
problematic.

After converting that to platform APIs you'll get janitor style cleanups
trying to convert to devm_platform_ioremap_resource(). We'll have to
discuss this again when that happens, even if there's a comment in the
code indicating we can't reserve the IO space because there's another
driver. These problems have happened in the past, fun times!

Furthermore, in DT, reg properties aren't supposed to overlap. When that
happens it usually indicates the DT is being written to describe driver
structure instead of the IP blocks that are delivered by the hardware
engineer. In this case it sounds like a combined clk and reset IP block
because they piled all the SoC glue stuff into a register range. Are
there more features in this IO range?
Tomer Maimon July 24, 2022, 9:06 a.m. UTC | #2
Hi Stephen,

Thanks for your detailed explanation!

On Sat, 23 Jul 2022 at 06:02, Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting Tomer Maimon (2022-07-19 03:04:43)
> > On Mon, 18 Jul 2022 at 22:14, Stephen Boyd <sboyd@kernel.org> wrote:
> > >
> > >
> > > So the clk and reset driver should be the same driver, or one driver
> > > should register the other and use the auxiliary bus to express the
> > > relationship. That way we know that the drivers are tightly coupled and
> > > aren't going to stomp over each other.
> > I think it is very problematic to use the same driver for the reset
> > and the clocks also because The NPCM reset driver is an old driver
> > that was used also to the older NPCM BMC SoC so it will be problematic
> > to use the clock and reset driver in the same space.
> > indeed the reset and clocks are using the same memory region but they
> > are not using the same registers, is it not enough?
> > Please be aware that the NPCM reset driver is checking that it is
> > using the reset registers before calling I/O functions.
>
> To put it simply, platform device drivers should use platform device
> APIs. The platform device APIs hide the fact that the firmware is ACPI
> or DT or nothing at all. The usage of of_address_to_resource() is
> problematic.
>
> After converting that to platform APIs you'll get janitor style cleanups
> trying to convert to devm_platform_ioremap_resource(). We'll have to
> discuss this again when that happens, even if there's a comment in the
> code indicating we can't reserve the IO space because there's another
> driver. These problems have happened in the past, fun times!
>
> Furthermore, in DT, reg properties aren't supposed to overlap. When that
> happens it usually indicates the DT is being written to describe driver
> structure instead of the IP blocks that are delivered by the hardware
> engineer. In this case it sounds like a combined clk and reset IP block
> because they piled all the SoC glue stuff into a register range. Are
> there more features in this IO range?

No, this range only combined the reset and clock together, but it
combined in a way that we cannot split it to two or even three
different registers...

I do see a way to combine the clock and the reset driver, the NPCM
reset driver is serving other NPCM BMC's.
Should we use regmap to handle the clock registers instead of ioremap?

Best regards,

Tomer
Stephen Boyd July 29, 2022, 10:56 p.m. UTC | #3
Quoting Tomer Maimon (2022-07-24 02:06:54)
> On Sat, 23 Jul 2022 at 06:02, Stephen Boyd <sboyd@kernel.org> wrote:
> > Furthermore, in DT, reg properties aren't supposed to overlap. When that
> > happens it usually indicates the DT is being written to describe driver
> > structure instead of the IP blocks that are delivered by the hardware
> > engineer. In this case it sounds like a combined clk and reset IP block
> > because they piled all the SoC glue stuff into a register range. Are
> > there more features in this IO range?
> 
> No, this range only combined the reset and clock together, but it
> combined in a way that we cannot split it to two or even three
> different registers...

Because it is jumbled in some range?

> 
> I do see a way to combine the clock and the reset driver, the NPCM
> reset driver is serving other NPCM BMC's.
> Should we use regmap to handle the clock registers instead of ioremap?

Sure? Using regmap or not looks like a parallel discussion. How does it
help use platform APIs?
Stephen Boyd Aug. 9, 2022, 6:02 p.m. UTC | #4
Quoting Tomer Maimon (2022-08-08 06:08:08)
> On Mon, 8 Aug 2022 at 15:37, Tomer Maimon <tmaimon77@gmail.com> wrote:
> > > Using platform APIs means using platform_*() functions, not of_*()
> > > functions, which are open-firmware/DT related. Regmap can be used to
> > > operate on registers mapped as __iomem, which is different from platform
> > > APIs.
> > I will use platform_get_resource() and devm_ioremap_resource()
> > functions in the next version.
> I will use platform_get_resource() and ioremap() function next
> veriosn, is it fine?

As stated earlier it will work for now but eventually you'll get patches
from janitors trying to convert to a devm based API that reserves the
register region. Can you ioremap the register once and register an
auxiliary device and driver for the reset (or clk) part so that the
driver can be moved out to the drivers/reset/ path?