| Message ID | 20220629164414.301813-3-viorel.suman@oss.nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | dt-bindings: arm: freescale: Switch fsl,scu from txt to yaml | expand |
On 22-06-29 19:53:51, Krzysztof Kozlowski wrote: > On 29/06/2022 18:44, Viorel Suman (OSS) wrote: > > From: Abel Vesa <abel.vesa@nxp.com> > > > > In order to replace the fsl,scu txt file from bindings/arm/freescale, > > we need to split it between the right subsystems. This patch documents > > separately the 'iomux/pinctrl' child node of the SCU main node. > > > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > > Signed-off-by: Viorel Suman <viorel.suman@nxp.com> > > --- > > .../bindings/pinctrl/fsl,scu-pinctrl.yaml | 68 +++++++++++++++++++ > > 1 file changed, 68 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml > > new file mode 100644 > > index 000000000000..76a2e7b28172 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml [...] > > + fsl,pins: > > + description: > > + each entry consists of 3 integers and represents the pin ID, the mux value > > + and config setting for the pin. The first 2 integers - pin_id and mux_val - are > > + specified using a PIN_FUNC_ID macro, which can be found in > > + <include/dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer CONFIG is > > + the pad setting value like pull-up on this pin. Please refer to the > > + appropriate i.MX8 Reference Manual for detailed CONFIG settings. > > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > > Look at fsl,imx8mq-pinctrl.yaml. Each item is described (items under items). Added them initially, but later dropped because of some logs like "pinctrl@xxxxxxx: usdhc1grp:fsl,pins:0: [...] is too long" shown by "make dt_binding_check dtbs_check DT_SCHEMA_FILES=[...]/fsl,scu-pinctrl.yaml" Same logs are shown for "fsl,imx8mq-pinctrl.yaml". Will add the items description in the next version. Thank you, Viorel
On 30/06/2022 14:37, Viorel Suman (OSS) wrote: > On 22-06-29 19:53:51, Krzysztof Kozlowski wrote: >> On 29/06/2022 18:44, Viorel Suman (OSS) wrote: >>> From: Abel Vesa <abel.vesa@nxp.com> >>> >>> In order to replace the fsl,scu txt file from bindings/arm/freescale, >>> we need to split it between the right subsystems. This patch documents >>> separately the 'iomux/pinctrl' child node of the SCU main node. >>> >>> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> >>> Signed-off-by: Viorel Suman <viorel.suman@nxp.com> >>> --- >>> .../bindings/pinctrl/fsl,scu-pinctrl.yaml | 68 +++++++++++++++++++ >>> 1 file changed, 68 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml >>> new file mode 100644 >>> index 000000000000..76a2e7b28172 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml > [...] >>> + fsl,pins: >>> + description: >>> + each entry consists of 3 integers and represents the pin ID, the mux value >>> + and config setting for the pin. The first 2 integers - pin_id and mux_val - are >>> + specified using a PIN_FUNC_ID macro, which can be found in >>> + <include/dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer CONFIG is >>> + the pad setting value like pull-up on this pin. Please refer to the >>> + appropriate i.MX8 Reference Manual for detailed CONFIG settings. >>> + $ref: /schemas/types.yaml#/definitions/uint32-matrix >> >> Look at fsl,imx8mq-pinctrl.yaml. Each item is described (items under items). > > Added them initially, but later dropped because of some logs like > "pinctrl@xxxxxxx: usdhc1grp:fsl,pins:0: [...] is too long" shown by > "make dt_binding_check dtbs_check DT_SCHEMA_FILES=[...]/fsl,scu-pinctrl.yaml" > > Same logs are shown for "fsl,imx8mq-pinctrl.yaml". Will add the items description in the next > version. > The fsl,imx8mq-pinctrl.yaml should be correct and I don't see the reason why dtschema complains in some of the entries. It's like one define was not correct... I'll take a look at this later, but anyway keep the same as fsl,imx8mq-pinctrl.yaml even if it complains. Best regards, Krzysztof
On Thu, Jun 30, 2022 at 12:33 PM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 30/06/2022 14:37, Viorel Suman (OSS) wrote: > > On 22-06-29 19:53:51, Krzysztof Kozlowski wrote: > >> On 29/06/2022 18:44, Viorel Suman (OSS) wrote: > >>> From: Abel Vesa <abel.vesa@nxp.com> > >>> > >>> In order to replace the fsl,scu txt file from bindings/arm/freescale, > >>> we need to split it between the right subsystems. This patch documents > >>> separately the 'iomux/pinctrl' child node of the SCU main node. > >>> > >>> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > >>> Signed-off-by: Viorel Suman <viorel.suman@nxp.com> > >>> --- > >>> .../bindings/pinctrl/fsl,scu-pinctrl.yaml | 68 +++++++++++++++++++ > >>> 1 file changed, 68 insertions(+) > >>> create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml > >>> > >>> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml > >>> new file mode 100644 > >>> index 000000000000..76a2e7b28172 > >>> --- /dev/null > >>> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml > > [...] > >>> + fsl,pins: > >>> + description: > >>> + each entry consists of 3 integers and represents the pin ID, the mux value > >>> + and config setting for the pin. The first 2 integers - pin_id and mux_val - are > >>> + specified using a PIN_FUNC_ID macro, which can be found in > >>> + <include/dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer CONFIG is > >>> + the pad setting value like pull-up on this pin. Please refer to the > >>> + appropriate i.MX8 Reference Manual for detailed CONFIG settings. > >>> + $ref: /schemas/types.yaml#/definitions/uint32-matrix > >> > >> Look at fsl,imx8mq-pinctrl.yaml. Each item is described (items under items). > > > > Added them initially, but later dropped because of some logs like > > "pinctrl@xxxxxxx: usdhc1grp:fsl,pins:0: [...] is too long" shown by > > "make dt_binding_check dtbs_check DT_SCHEMA_FILES=[...]/fsl,scu-pinctrl.yaml" > > > > Same logs are shown for "fsl,imx8mq-pinctrl.yaml". Will add the items description in the next > > version. > > > > The fsl,imx8mq-pinctrl.yaml should be correct and I don't see the reason > why dtschema complains in some of the entries. It's like one define was > not correct... I'll take a look at this later, but anyway keep the same > as fsl,imx8mq-pinctrl.yaml even if it complains. The issue is that 'fsl,pins' is problematic for the new dtb decoding because it has a variable definition in terms of matrix bounds as each i.MX platform has its own length (typ 5 or 6). The tools try to work around it by figuring out which size fits. That works until there are multiple answers which seems to be what's happening here. The easiest solution I think is to just strip the constraints in occurances of this property. I'll look into that. Rob
On Tue, Jul 5, 2022 at 12:33 PM Rob Herring <robh+dt@kernel.org> wrote: > > On Thu, Jun 30, 2022 at 12:33 PM Krzysztof Kozlowski > <krzysztof.kozlowski@linaro.org> wrote: > > > > On 30/06/2022 14:37, Viorel Suman (OSS) wrote: > > > On 22-06-29 19:53:51, Krzysztof Kozlowski wrote: > > >> On 29/06/2022 18:44, Viorel Suman (OSS) wrote: > > >>> From: Abel Vesa <abel.vesa@nxp.com> > > >>> > > >>> In order to replace the fsl,scu txt file from bindings/arm/freescale, > > >>> we need to split it between the right subsystems. This patch documents > > >>> separately the 'iomux/pinctrl' child node of the SCU main node. > > >>> > > >>> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > > >>> Signed-off-by: Viorel Suman <viorel.suman@nxp.com> > > >>> --- > > >>> .../bindings/pinctrl/fsl,scu-pinctrl.yaml | 68 +++++++++++++++++++ > > >>> 1 file changed, 68 insertions(+) > > >>> create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml > > >>> > > >>> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml > > >>> new file mode 100644 > > >>> index 000000000000..76a2e7b28172 > > >>> --- /dev/null > > >>> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml > > > [...] > > >>> + fsl,pins: > > >>> + description: > > >>> + each entry consists of 3 integers and represents the pin ID, the mux value > > >>> + and config setting for the pin. The first 2 integers - pin_id and mux_val - are > > >>> + specified using a PIN_FUNC_ID macro, which can be found in > > >>> + <include/dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer CONFIG is > > >>> + the pad setting value like pull-up on this pin. Please refer to the > > >>> + appropriate i.MX8 Reference Manual for detailed CONFIG settings. > > >>> + $ref: /schemas/types.yaml#/definitions/uint32-matrix > > >> > > >> Look at fsl,imx8mq-pinctrl.yaml. Each item is described (items under items). > > > > > > Added them initially, but later dropped because of some logs like > > > "pinctrl@xxxxxxx: usdhc1grp:fsl,pins:0: [...] is too long" shown by > > > "make dt_binding_check dtbs_check DT_SCHEMA_FILES=[...]/fsl,scu-pinctrl.yaml" > > > > > > Same logs are shown for "fsl,imx8mq-pinctrl.yaml". Will add the items description in the next > > > version. > > > > > > > The fsl,imx8mq-pinctrl.yaml should be correct and I don't see the reason > > why dtschema complains in some of the entries. It's like one define was > > not correct... I'll take a look at this later, but anyway keep the same > > as fsl,imx8mq-pinctrl.yaml even if it complains. > > The issue is that 'fsl,pins' is problematic for the new dtb decoding > because it has a variable definition in terms of matrix bounds as each > i.MX platform has its own length (typ 5 or 6). The tools try to work > around it by figuring out which size fits. That works until there are > multiple answers which seems to be what's happening here. > > The easiest solution I think is to just strip the constraints in > occurances of this property. I'll look into that. This is now fixed in the dt-schema main branch. Rob
On 06/07/2022 16:11, Rob Herring wrote: >>> The fsl,imx8mq-pinctrl.yaml should be correct and I don't see the reason >>> why dtschema complains in some of the entries. It's like one define was >>> not correct... I'll take a look at this later, but anyway keep the same >>> as fsl,imx8mq-pinctrl.yaml even if it complains. >> >> The issue is that 'fsl,pins' is problematic for the new dtb decoding >> because it has a variable definition in terms of matrix bounds as each >> i.MX platform has its own length (typ 5 or 6). The tools try to work >> around it by figuring out which size fits. That works until there are >> multiple answers which seems to be what's happening here. >> >> The easiest solution I think is to just strip the constraints in >> occurances of this property. I'll look into that. > > This is now fixed in the dt-schema main branch. Great, thanks! Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml new file mode 100644 index 000000000000..76a2e7b28172 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,scu-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX SCU Client Device Node - Pinctrl bindings based on SCU Message Protocol + +maintainers: + - Dong Aisheng <aisheng.dong@nxp.com> + +description: i.MX SCU Client Device Node + Client nodes are maintained as children of the relevant IMX-SCU device node. + This binding uses the i.MX common pinctrl binding. + (Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt) + +allOf: + - $ref: "pinctrl.yaml#" + +properties: + compatible: + enum: + - fsl,imx8qm-iomuxc + - fsl,imx8qxp-iomuxc + - fsl,imx8dxl-iomuxc + +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 3 integers and represents the pin ID, the mux value + and config setting for the pin. The first 2 integers - pin_id and mux_val - are + specified using a PIN_FUNC_ID macro, which can be found in + <include/dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to the + appropriate i.MX8 Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/pads-imx8qxp.h> + + pinctrl { + compatible = "fsl,imx8qxp-iomuxc"; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + 111 0 0x06000020 + 112 0 0x06000020 + >; + }; + };