| Message ID | 20220608105238.2973600-1-dmitry.baryshkov@linaro.org |
|---|---|
| Headers | show |
| Series | PCI: qcom: Rework pipe_clk/pipe_clk_src handling | expand |
Quoting Dmitry Baryshkov (2022-06-08 03:52:34) > On recent Qualcomm platforms the QMP PIPE clocks feed into a set of > muxes which must be parked to the "safe" source (bi_tcxo) when > corresponding GDSC is turned off and on again. Currently this is > handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src > clock. However the same code sequence should be applied in the > pcie-qcom endpoint, USB3 and UFS drivers. > > Rather than copying this sequence over and over again, follow the > example of clk_rcg2_shared_ops and implement this parking in the > enable() and disable() clock operations. Supplement the regmap-mux with > the new clk_regmap_phy_mux type, which implements such multiplexers > as a simple gate clocks. > > This is possible since each of these multiplexers has just two clock > sources: one coming from the PHY and a reference (XO) one. If the clock > is running off the from-PHY source, report it as enabled. Report it as > disabled otherwise (if it uses reference source). > > This way the PHY will disable the pipe clock before turning off the > GDSC, which in turn would lead to disabling corresponding pipe_clk_src > (and thus it being parked to a safe, reference clock source). And vice > versa, after enabling the GDSC the PHY will enable the pipe clock, which > would cause pipe_clk_src to be switched from a safe source to the > working one. > > Reviewed-by: Johan Hovold <johan+linaro@kernel.org> > Tested-by: Johan Hovold <johan+linaro@kernel.org> > Reported-by: kernel test robot <lkp@intel.com> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Quoting Dmitry Baryshkov (2022-06-08 03:52:36) > Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let > the clock framework automatically park the clock when the clock is > switched off and restore the parent when the clock is switched on. > > Reviewed-by: Johan Hovold <johan+linaro@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Quoting Dmitry Baryshkov (2022-06-08 03:52:37) > PCIe PHY drivers (both QMP and PCIe2) already do clk_prepare_enable() / > clk_prepare_disable() pipe_clk. Remove extra calls to enable/disable > this clock from the PCIe driver, so that the PHY driver can manage the > clock on its own. > > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > Reviewed-by: Johan Hovold <johan+linaro@kernel.org> > Tested-by: Johan Hovold <johan+linaro@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Stephen Boyd <sboyd@kernel.org>
On Wed, Jun 08, 2022 at 01:52:33PM +0300, Dmitry Baryshkov wrote: > PCIe pipe clk (and some other clocks) must be parked to the "safe" > source (bi_tcxo) when corresponding GDSC is turned off and on again. > Currently this is handcoded in the PCIe driver by reparenting the > gcc_pipe_N_clk_src clock. > > Instead of doing it manually, follow the approach used by > clk_rcg2_shared_ops and implement this parking in the enable() and > disable() clock operations for respective pipe clocks. > > Changes since v10: > - Added linux/bitfield.h include (lkp) > - Split fw_name/name lines in the gcc-sm8450.c (Johan) > > Changes since v9: > - Respin fixing Tested-by tags, no code changes > > Changes since v8: > - Readded .name to changed entries in gcc-sc7280 driver to restore > compatibility with older DTS, > - Rebased on top of linux-next, dropping reverts, > - Verified to include all R-b tags (excuse me, Johan, I missed them > in the previous iteration). > > Changes since v7: > - Brought back the struct clk_regmap_phy_mux (Johan) > - Fixed includes (Stephen) > - Dropped CLK_SET_RATE_PARENT flags from changed pipe clocks, they are > not set in the current code and they are useless as the PHY's clock > has fixed rate. > > Changes since v6: > - Switched the ops to use GENMASK/FIELD_GET/FIELD_PUT (Stephen), > - As all pipe/symbol clock source clocks have the same register (and > parents) layout, hardcode all the values. If the need arises, this > can be changed later (Stephen), > - Fixed commit messages and comments (suggested by Johan), > - Added revert for the clk_regmap_mux_safe that have been already > picked up by Bjorn. > > Changes since v5: > - Rename the clock to clk-regmap-phy-mux and the enable/disable values > to phy_src_val and ref_src_val respectively (as recommended by > Johan). > > Changes since v4: > - Renamed the clock to clk-regmap-pipe-src, > - Added mention of PCIe2 PHY to the commit message, > - Expanded commit messages to mention additional pipe clock details. > > Changes since v3: > - Replaced the clock multiplexer implementation with branch-like clock. > > Changes since v2: > - Added is_enabled() callback > - Added default parent to the pipe clock configuration > > Changes since v1: > - Rebased on top of [1]. > - Removed erroneous Fixes tag from the patch 4. > > Changes since RFC: > - Rework clk-regmap-mux fields. Specify safe parent as P_* value rather > than specifying the register value directly > - Expand commit message to the first patch to specially mention that > it is required only on newer generations of Qualcomm chipsets. > > Dmitry Baryshkov (5): > clk: qcom: regmap: add PHY clock source implementation > clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe > clocks > clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe > clocks > PCI: qcom: Remove unnecessary pipe_clk handling > PCI: qcom: Drop manual pipe_clk_src handling > > > Dmitry Baryshkov (5): > clk: qcom: regmap: add PHY clock source implementation > clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe > clocks > clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe > clocks > PCI: qcom: Remove unnecessary pipe_clk handling > PCI: qcom: Drop manual pipe_clk_src handling > > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/clk-regmap-phy-mux.c | 62 ++++++++++++++++++++ > drivers/clk/qcom/clk-regmap-phy-mux.h | 33 +++++++++++ > drivers/clk/qcom/gcc-sc7280.c | 49 +++++----------- > drivers/clk/qcom/gcc-sm8450.c | 49 +++++----------- > drivers/pci/controller/dwc/pcie-qcom.c | 81 +------------------------- > 6 files changed, 127 insertions(+), 148 deletions(-) > create mode 100644 drivers/clk/qcom/clk-regmap-phy-mux.c > create mode 100644 drivers/clk/qcom/clk-regmap-phy-mux.h I applied this to pci/ctrl/qcom for v5.20, thanks! Clock folks (Bjorn A, Andy, Michael, Stephen), I assume you're OK with these being merged via the PCI tree. Let me know if you prefer anything different.
On Wed, 8 Jun 2022 13:52:33 +0300, Dmitry Baryshkov wrote: > PCIe pipe clk (and some other clocks) must be parked to the "safe" > source (bi_tcxo) when corresponding GDSC is turned off and on again. > Currently this is handcoded in the PCIe driver by reparenting the > gcc_pipe_N_clk_src clock. > > Instead of doing it manually, follow the approach used by > clk_rcg2_shared_ops and implement this parking in the enable() and > disable() clock operations for respective pipe clocks. > > [...] Applied, thanks! [1/5] clk: qcom: regmap: add PHY clock source implementation commit: 74e4190cdebe5a4aa099185edb4db418fc9883e3 [2/5] clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks commit: 7ee9d2e8b9c9f4a829cd2d77c8cba36c514f24ba [3/5] clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe clocks commit: 553d12b20c10953617cc195f9e447a177c776f9d Best regards,
Hi, On 16/06/2022 21:21, Bjorn Helgaas wrote: > On Wed, Jun 08, 2022 at 01:52:33PM +0300, Dmitry Baryshkov wrote: >> PCIe pipe clk (and some other clocks) must be parked to the "safe" >> source (bi_tcxo) when corresponding GDSC is turned off and on again. >> Currently this is handcoded in the PCIe driver by reparenting the >> gcc_pipe_N_clk_src clock. >> >> Instead of doing it manually, follow the approach used by >> clk_rcg2_shared_ops and implement this parking in the enable() and >> disable() clock operations for respective pipe clocks. >> >> Changes since v10: >> - Added linux/bitfield.h include (lkp) >> - Split fw_name/name lines in the gcc-sm8450.c (Johan) >> >> Changes since v9: >> - Respin fixing Tested-by tags, no code changes >> >> Changes since v8: >> - Readded .name to changed entries in gcc-sc7280 driver to restore >> compatibility with older DTS, >> - Rebased on top of linux-next, dropping reverts, >> - Verified to include all R-b tags (excuse me, Johan, I missed them >> in the previous iteration). >> >> Changes since v7: >> - Brought back the struct clk_regmap_phy_mux (Johan) >> - Fixed includes (Stephen) >> - Dropped CLK_SET_RATE_PARENT flags from changed pipe clocks, they are >> not set in the current code and they are useless as the PHY's clock >> has fixed rate. >> >> Changes since v6: >> - Switched the ops to use GENMASK/FIELD_GET/FIELD_PUT (Stephen), >> - As all pipe/symbol clock source clocks have the same register (and >> parents) layout, hardcode all the values. If the need arises, this >> can be changed later (Stephen), >> - Fixed commit messages and comments (suggested by Johan), >> - Added revert for the clk_regmap_mux_safe that have been already >> picked up by Bjorn. >> >> Changes since v5: >> - Rename the clock to clk-regmap-phy-mux and the enable/disable values >> to phy_src_val and ref_src_val respectively (as recommended by >> Johan). >> >> Changes since v4: >> - Renamed the clock to clk-regmap-pipe-src, >> - Added mention of PCIe2 PHY to the commit message, >> - Expanded commit messages to mention additional pipe clock details. >> >> Changes since v3: >> - Replaced the clock multiplexer implementation with branch-like clock. >> >> Changes since v2: >> - Added is_enabled() callback >> - Added default parent to the pipe clock configuration >> >> Changes since v1: >> - Rebased on top of [1]. >> - Removed erroneous Fixes tag from the patch 4. >> >> Changes since RFC: >> - Rework clk-regmap-mux fields. Specify safe parent as P_* value rather >> than specifying the register value directly >> - Expand commit message to the first patch to specially mention that >> it is required only on newer generations of Qualcomm chipsets. >> >> Dmitry Baryshkov (5): >> clk: qcom: regmap: add PHY clock source implementation >> clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe >> clocks >> clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe >> clocks >> PCI: qcom: Remove unnecessary pipe_clk handling >> PCI: qcom: Drop manual pipe_clk_src handling >> >> >> Dmitry Baryshkov (5): >> clk: qcom: regmap: add PHY clock source implementation >> clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe >> clocks >> clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe >> clocks >> PCI: qcom: Remove unnecessary pipe_clk handling >> PCI: qcom: Drop manual pipe_clk_src handling >> >> drivers/clk/qcom/Makefile | 1 + >> drivers/clk/qcom/clk-regmap-phy-mux.c | 62 ++++++++++++++++++++ >> drivers/clk/qcom/clk-regmap-phy-mux.h | 33 +++++++++++ >> drivers/clk/qcom/gcc-sc7280.c | 49 +++++----------- >> drivers/clk/qcom/gcc-sm8450.c | 49 +++++----------- >> drivers/pci/controller/dwc/pcie-qcom.c | 81 +------------------------- >> 6 files changed, 127 insertions(+), 148 deletions(-) >> create mode 100644 drivers/clk/qcom/clk-regmap-phy-mux.c >> create mode 100644 drivers/clk/qcom/clk-regmap-phy-mux.h > > I applied this to pci/ctrl/qcom for v5.20, thanks! > > Clock folks (Bjorn A, Andy, Michael, Stephen), I assume you're OK with > these being merged via the PCI tree. Let me know if you prefer > anything different. I noticed that this patchset is not a part of linux-next. Is it still pending to be merged in 5.20?
Hi Dmitry, On 6/8/22 13:52, Dmitry Baryshkov wrote: > PCIe PHY drivers (both QMP and PCIe2) already do clk_prepare_enable() / > clk_prepare_disable() pipe_clk. Remove extra calls to enable/disable > this clock from the PCIe driver, so that the PHY driver can manage the > clock on its own. > > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > Reviewed-by: Johan Hovold <johan+linaro@kernel.org> > Tested-by: Johan Hovold <johan+linaro@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 44 ++------------------------ > 1 file changed, 3 insertions(+), 41 deletions(-) > I'm very happy to see that is gone. Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
PCIe pipe clk (and some other clocks) must be parked to the "safe" source (bi_tcxo) when corresponding GDSC is turned off and on again. Currently this is handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src clock. Instead of doing it manually, follow the approach used by clk_rcg2_shared_ops and implement this parking in the enable() and disable() clock operations for respective pipe clocks. Changes since v10: - Added linux/bitfield.h include (lkp) - Split fw_name/name lines in the gcc-sm8450.c (Johan) Changes since v9: - Respin fixing Tested-by tags, no code changes Changes since v8: - Readded .name to changed entries in gcc-sc7280 driver to restore compatibility with older DTS, - Rebased on top of linux-next, dropping reverts, - Verified to include all R-b tags (excuse me, Johan, I missed them in the previous iteration). Changes since v7: - Brought back the struct clk_regmap_phy_mux (Johan) - Fixed includes (Stephen) - Dropped CLK_SET_RATE_PARENT flags from changed pipe clocks, they are not set in the current code and they are useless as the PHY's clock has fixed rate. Changes since v6: - Switched the ops to use GENMASK/FIELD_GET/FIELD_PUT (Stephen), - As all pipe/symbol clock source clocks have the same register (and parents) layout, hardcode all the values. If the need arises, this can be changed later (Stephen), - Fixed commit messages and comments (suggested by Johan), - Added revert for the clk_regmap_mux_safe that have been already picked up by Bjorn. Changes since v5: - Rename the clock to clk-regmap-phy-mux and the enable/disable values to phy_src_val and ref_src_val respectively (as recommended by Johan). Changes since v4: - Renamed the clock to clk-regmap-pipe-src, - Added mention of PCIe2 PHY to the commit message, - Expanded commit messages to mention additional pipe clock details. Changes since v3: - Replaced the clock multiplexer implementation with branch-like clock. Changes since v2: - Added is_enabled() callback - Added default parent to the pipe clock configuration Changes since v1: - Rebased on top of [1]. - Removed erroneous Fixes tag from the patch 4. Changes since RFC: - Rework clk-regmap-mux fields. Specify safe parent as P_* value rather than specifying the register value directly - Expand commit message to the first patch to specially mention that it is required only on newer generations of Qualcomm chipsets. Dmitry Baryshkov (5): clk: qcom: regmap: add PHY clock source implementation clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe clocks PCI: qcom: Remove unnecessary pipe_clk handling PCI: qcom: Drop manual pipe_clk_src handling Dmitry Baryshkov (5): clk: qcom: regmap: add PHY clock source implementation clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe clocks PCI: qcom: Remove unnecessary pipe_clk handling PCI: qcom: Drop manual pipe_clk_src handling drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-regmap-phy-mux.c | 62 ++++++++++++++++++++ drivers/clk/qcom/clk-regmap-phy-mux.h | 33 +++++++++++ drivers/clk/qcom/gcc-sc7280.c | 49 +++++----------- drivers/clk/qcom/gcc-sm8450.c | 49 +++++----------- drivers/pci/controller/dwc/pcie-qcom.c | 81 +------------------------- 6 files changed, 127 insertions(+), 148 deletions(-) create mode 100644 drivers/clk/qcom/clk-regmap-phy-mux.c create mode 100644 drivers/clk/qcom/clk-regmap-phy-mux.h