| Message ID | cover.1644234441.git.baruch@tkos.co.il |
|---|---|
| Headers | show |
| Series | PCI: IPQ6018 platform support | expand |
On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote: > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is > ported from downstream Codeaurora v5.4 kernel. The main difference from > downstream code is the split of PCIe registers configuration from .init to > .post_init, since it requires phy_power_on(). > > Tested on IPQ6010 based hardware. > > Changes in v6: > > * Drop DT patch applied to the qcom tree > > * Normalize driver changes subject line > > * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, > and define it using PCI_EXP_SLTCAP_* macros > > * Drop a vague comment about ASPM configuration > > * Add a comment about the source of delay periods > > Changes in v5: > > * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson) > > Changes in v4: > > * Drop applied DT bits > > * Add max-link-speed that was missing from the applied v2 patch > > * Rebase the driver on v5.16-rc3 > > Changes in v3: > > * Drop applied patches > > * Rely on generic code for speed setup > > * Drop unused macros > > * Formatting fixes > > Changes in v2: > > * Add patch moving GEN3_RELATED macros to a common header > > * Drop ATU configuration from pcie-qcom > > * Remove local definition of common registers > > * Use bulk clk and reset APIs > > * Remove msi-parent from device-tree > > Baruch Siach (2): > PCI: dwc: tegra: move GEN3_RELATED DBI register to common header > PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* > > Selvam Sathappan Periakaruppan (1): > PCI: qcom: Add IPQ60xx support > > drivers/pci/controller/dwc/pcie-designware.h | 7 + > drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++- > drivers/pci/controller/dwc/pcie-tegra194.c | 6 - > 3 files changed, 160 insertions(+), 8 deletions(-) Bjorn, Andy, Can you ACK please if this series is ready to be merged ? Thanks, Lorenzo
On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote: > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is > ported from downstream Codeaurora v5.4 kernel. The main difference from > downstream code is the split of PCIe registers configuration from .init to > .post_init, since it requires phy_power_on(). > > Tested on IPQ6010 based hardware. > > Changes in v6: > > * Drop DT patch applied to the qcom tree > > * Normalize driver changes subject line > > * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, > and define it using PCI_EXP_SLTCAP_* macros > > * Drop a vague comment about ASPM configuration > > * Add a comment about the source of delay periods > > Changes in v5: > > * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson) > > Changes in v4: > > * Drop applied DT bits > > * Add max-link-speed that was missing from the applied v2 patch > > * Rebase the driver on v5.16-rc3 > > Changes in v3: > > * Drop applied patches > > * Rely on generic code for speed setup > > * Drop unused macros > > * Formatting fixes > > Changes in v2: > > * Add patch moving GEN3_RELATED macros to a common header > > * Drop ATU configuration from pcie-qcom > > * Remove local definition of common registers > > * Use bulk clk and reset APIs > > * Remove msi-parent from device-tree > > Baruch Siach (2): > PCI: dwc: tegra: move GEN3_RELATED DBI register to common header > PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* > > Selvam Sathappan Periakaruppan (1): > PCI: qcom: Add IPQ60xx support > > drivers/pci/controller/dwc/pcie-designware.h | 7 + > drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++- > drivers/pci/controller/dwc/pcie-tegra194.c | 6 - > 3 files changed, 160 insertions(+), 8 deletions(-) Hi Bjorn, Andy, any feedback on this series please ? Thanks, Lorenzo
On Tue, Apr 12, 2022 at 05:12:59PM +0100, Lorenzo Pieralisi wrote: > On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote: > > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is > > ported from downstream Codeaurora v5.4 kernel. The main difference from > > downstream code is the split of PCIe registers configuration from .init to > > .post_init, since it requires phy_power_on(). > > > > Tested on IPQ6010 based hardware. > > > > Changes in v6: > > > > * Drop DT patch applied to the qcom tree > > > > * Normalize driver changes subject line > > > > * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, > > and define it using PCI_EXP_SLTCAP_* macros > > > > * Drop a vague comment about ASPM configuration > > > > * Add a comment about the source of delay periods > > > > Changes in v5: > > > > * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson) > > > > Changes in v4: > > > > * Drop applied DT bits > > > > * Add max-link-speed that was missing from the applied v2 patch > > > > * Rebase the driver on v5.16-rc3 > > > > Changes in v3: > > > > * Drop applied patches > > > > * Rely on generic code for speed setup > > > > * Drop unused macros > > > > * Formatting fixes > > > > Changes in v2: > > > > * Add patch moving GEN3_RELATED macros to a common header > > > > * Drop ATU configuration from pcie-qcom > > > > * Remove local definition of common registers > > > > * Use bulk clk and reset APIs > > > > * Remove msi-parent from device-tree > > > > Baruch Siach (2): > > PCI: dwc: tegra: move GEN3_RELATED DBI register to common header > > PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* > > > > Selvam Sathappan Periakaruppan (1): > > PCI: qcom: Add IPQ60xx support > > > > drivers/pci/controller/dwc/pcie-designware.h | 7 + > > drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++- > > drivers/pci/controller/dwc/pcie-tegra194.c | 6 - > > 3 files changed, 160 insertions(+), 8 deletions(-) > > Hi Bjorn, Andy, > > any feedback on this series please ? Any feedback on these patches please ? Thanks, Lorenzo
On Wed, May 11, 2022 at 4:03 PM Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote: > > On Tue, Apr 12, 2022 at 05:12:59PM +0100, Lorenzo Pieralisi wrote: > > On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote: > > > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is > > > ported from downstream Codeaurora v5.4 kernel. The main difference from > > > downstream code is the split of PCIe registers configuration from .init to > > > .post_init, since it requires phy_power_on(). > > > > > > Tested on IPQ6010 based hardware. > > > > > > Changes in v6: > > > > > > * Drop DT patch applied to the qcom tree > > > > > > * Normalize driver changes subject line > > > > > > * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, > > > and define it using PCI_EXP_SLTCAP_* macros > > > > > > * Drop a vague comment about ASPM configuration > > > > > > * Add a comment about the source of delay periods > > > > > > Changes in v5: > > > > > > * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson) > > > > > > Changes in v4: > > > > > > * Drop applied DT bits > > > > > > * Add max-link-speed that was missing from the applied v2 patch > > > > > > * Rebase the driver on v5.16-rc3 > > > > > > Changes in v3: > > > > > > * Drop applied patches > > > > > > * Rely on generic code for speed setup > > > > > > * Drop unused macros > > > > > > * Formatting fixes > > > > > > Changes in v2: > > > > > > * Add patch moving GEN3_RELATED macros to a common header > > > > > > * Drop ATU configuration from pcie-qcom > > > > > > * Remove local definition of common registers > > > > > > * Use bulk clk and reset APIs > > > > > > * Remove msi-parent from device-tree > > > > > > Baruch Siach (2): > > > PCI: dwc: tegra: move GEN3_RELATED DBI register to common header > > > PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* > > > > > > Selvam Sathappan Periakaruppan (1): > > > PCI: qcom: Add IPQ60xx support > > > > > > drivers/pci/controller/dwc/pcie-designware.h | 7 + > > > drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++- > > > drivers/pci/controller/dwc/pcie-tegra194.c | 6 - > > > 3 files changed, 160 insertions(+), 8 deletions(-) > > > > Hi Bjorn, Andy, > > > > any feedback on this series please ? > > Any feedback on these patches please ? Finally dug the CP01, and for me, it works, so: Tested-by: Robert Marko <robert.marko@sartura.hr> Can we finally get this merged or at least looked at. IPQ8074 will also benefit from this. Regards, Robert > > Thanks, > Lorenzo
[+cc Stanimir, beginning of thread at https://lore.kernel.org/r/cover.1644234441.git.baruch@tkos.co.il] On Tue, Jun 07, 2022 at 03:12:19PM +0200, Robert Marko wrote: > On Wed, May 11, 2022 at 4:03 PM Lorenzo Pieralisi > <lorenzo.pieralisi@arm.com> wrote: > > > > On Tue, Apr 12, 2022 at 05:12:59PM +0100, Lorenzo Pieralisi wrote: > > > On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote: > > > > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is > > > > ported from downstream Codeaurora v5.4 kernel. The main difference from > > > > downstream code is the split of PCIe registers configuration from .init to > > > > .post_init, since it requires phy_power_on(). > > > > > > > > Tested on IPQ6010 based hardware. > > > > > > > > Changes in v6: > > > > > > > > * Drop DT patch applied to the qcom tree > > > > > > > > * Normalize driver changes subject line > > > > > > > > * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, > > > > and define it using PCI_EXP_SLTCAP_* macros > > > > > > > > * Drop a vague comment about ASPM configuration > > > > > > > > * Add a comment about the source of delay periods > > > > > > > > Changes in v5: > > > > > > > > * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson) > > > > > > > > Changes in v4: > > > > > > > > * Drop applied DT bits > > > > > > > > * Add max-link-speed that was missing from the applied v2 patch > > > > > > > > * Rebase the driver on v5.16-rc3 > > > > > > > > Changes in v3: > > > > > > > > * Drop applied patches > > > > > > > > * Rely on generic code for speed setup > > > > > > > > * Drop unused macros > > > > > > > > * Formatting fixes > > > > > > > > Changes in v2: > > > > > > > > * Add patch moving GEN3_RELATED macros to a common header > > > > > > > > * Drop ATU configuration from pcie-qcom > > > > > > > > * Remove local definition of common registers > > > > > > > > * Use bulk clk and reset APIs > > > > > > > > * Remove msi-parent from device-tree > > > > > > > > Baruch Siach (2): > > > > PCI: dwc: tegra: move GEN3_RELATED DBI register to common header > > > > PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* > > > > > > > > Selvam Sathappan Periakaruppan (1): > > > > PCI: qcom: Add IPQ60xx support > > > > > > > > drivers/pci/controller/dwc/pcie-designware.h | 7 + > > > > drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++- > > > > drivers/pci/controller/dwc/pcie-tegra194.c | 6 - > > > > 3 files changed, 160 insertions(+), 8 deletions(-) > > > > > > Hi Bjorn, Andy, > > > > > > any feedback on this series please ? > > > > Any feedback on these patches please ? > > Finally dug the CP01, and for me, it works, so: > Tested-by: Robert Marko <robert.marko@sartura.hr> This mainly affects pcie-qcom.c, so it looks like Stanimir should have been copied on this, but wasn't. Please include him on the next iteration. This will also need to be updated to apply on v5.19-rc1: 03:21:47 ~/linux (next)$ git checkout -b wip/baruch-ipq6018-v6 v5.19-rc1 Switched to a new branch 'wip/baruch-ipq6018-v6' 03:21:55 ~/linux (wip/baruch-ipq6018-v6)$ git am m/v6_20220207_baruch_pci_ipq6018_platform_support.mbx Applying: PCI: dwc: tegra: move GEN3_RELATED DBI register to common header Applying: PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* Applying: PCI: qcom: Add IPQ60xx support error: patch failed: drivers/pci/controller/dwc/pcie-qcom.c:1531 error: drivers/pci/controller/dwc/pcie-qcom.c: patch does not apply Patch failed at 0003 PCI: qcom: Add IPQ60xx support
This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on(). Tested on IPQ6010 based hardware. Changes in v6: * Drop DT patch applied to the qcom tree * Normalize driver changes subject line * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, and define it using PCI_EXP_SLTCAP_* macros * Drop a vague comment about ASPM configuration * Add a comment about the source of delay periods Changes in v5: * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson) Changes in v4: * Drop applied DT bits * Add max-link-speed that was missing from the applied v2 patch * Rebase the driver on v5.16-rc3 Changes in v3: * Drop applied patches * Rely on generic code for speed setup * Drop unused macros * Formatting fixes Changes in v2: * Add patch moving GEN3_RELATED macros to a common header * Drop ATU configuration from pcie-qcom * Remove local definition of common registers * Use bulk clk and reset APIs * Remove msi-parent from device-tree Baruch Siach (2): PCI: dwc: tegra: move GEN3_RELATED DBI register to common header PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* Selvam Sathappan Periakaruppan (1): PCI: qcom: Add IPQ60xx support drivers/pci/controller/dwc/pcie-designware.h | 7 + drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++- drivers/pci/controller/dwc/pcie-tegra194.c | 6 - 3 files changed, 160 insertions(+), 8 deletions(-)