| Message ID | 20220420025450.289578-7-yoshihiro.shimoda.uh@renesas.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | treewide: scsi: ufs: Add support for Renesas R-Car UFS controller | expand |
Hi Shimoda-san, On Wed, Apr 20, 2022 at 10:31 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Add UFS node for R-Car S4-8 (r8a779f0). > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi > @@ -40,6 +40,13 @@ extalr_clk: extalr { > clock-frequency = <0>; > }; > > + ufs30_clk: ufs30-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + /* This value must be overridden by the board */ > + clock-frequency = <0>; > + }; This matches what we typically do for the PCIe reference clock, but relies on the currently-missing clock generator initialization in the boot loader stack. > + > pmu_a55 { > compatible = "arm,cortex-a55-pmu"; > interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; > @@ -258,6 +265,18 @@ i2c5: i2c@e66e0000 { > status = "disabled"; > }; > > + ufs: ufs@e6860000 { > + compatible = "renesas,r8a779f0-ufs"; > + reg = <0 0xe6860000 0 0x100>; > + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; The R-Car S4-8 interrupt mapping spreadsheet lists two interrupts. > + clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>; > + clock-names = "fck", "ref_clk"; > + freq-table-hz = <200000000 200000000>, <38400000 38400000>; > + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; > + resets = <&cpg 1514>; > + status = "disabled"; > + }; > + > scif3: serial@e6c50000 { > compatible = "renesas,scif-r8a779f0", > "renesas,rcar-gen4-scif", "renesas,scif"; The rest LGTM, so with the above resolved: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert-san, Thank you for your review! > From: Geert Uytterhoeven, Sent: Wednesday, April 27, 2022 10:14 PM > > On Wed, Apr 20, 2022 at 10:31 AM Yoshihiro Shimoda > <yoshihiro.shimoda.uh@renesas.com> wrote: > > Add UFS node for R-Car S4-8 (r8a779f0). > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > > --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi > > @@ -40,6 +40,13 @@ extalr_clk: extalr { > > clock-frequency = <0>; > > }; > > > > + ufs30_clk: ufs30-clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + /* This value must be overridden by the board */ > > + clock-frequency = <0>; > > + }; > > This matches what we typically do for the PCIe reference clock, > but relies on the currently-missing clock generator initialization > in the boot loader stack. Yes, that's true. On UFS, the ufshcd.c requires a ref_clk and this is for it. The driver will get "ref_clk" rate and check it by ufs_ref_clk_freqs[]. > > + > > pmu_a55 { > > compatible = "arm,cortex-a55-pmu"; > > interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; > > @@ -258,6 +265,18 @@ i2c5: i2c@e66e0000 { > > status = "disabled"; > > }; > > > > + ufs: ufs@e6860000 { > > + compatible = "renesas,r8a779f0-ufs"; > > + reg = <0 0xe6860000 0 0x100>; > > + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; > > The R-Car S4-8 interrupt mapping spreadsheet lists two interrupts. Oops. I'll add it. > > + clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>; > > + clock-names = "fck", "ref_clk"; > > + freq-table-hz = <200000000 200000000>, <38400000 38400000>; > > + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; > > + resets = <&cpg 1514>; > > + status = "disabled"; > > + }; > > + > > scif3: serial@e6c50000 { > > compatible = "renesas,scif-r8a779f0", > > "renesas,rcar-gen4-scif", "renesas,scif"; > > The rest LGTM, so with the above resolved: > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Thanks! Best regards, Yoshihiro Shimoda
Hi Geert-san, > From: Yoshihiro Shimoda, Sent: Thursday, April 28, 2022 3:54 PM > > > From: Geert Uytterhoeven, Sent: Wednesday, April 27, 2022 10:14 PM > > > > On Wed, Apr 20, 2022 at 10:31 AM Yoshihiro Shimoda > > <yoshihiro.shimoda.uh@renesas.com> wrote: > > > Add UFS node for R-Car S4-8 (r8a779f0). > > > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > > > > --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi > > > +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi > > > @@ -40,6 +40,13 @@ extalr_clk: extalr { > > > clock-frequency = <0>; > > > }; > > > > > > + ufs30_clk: ufs30-clk { > > > + compatible = "fixed-clock"; > > > + #clock-cells = <0>; > > > + /* This value must be overridden by the board */ > > > + clock-frequency = <0>; > > > + }; > > > > This matches what we typically do for the PCIe reference clock, > > but relies on the currently-missing clock generator initialization > > in the boot loader stack. > > Yes, that's true. > > On UFS, the ufshcd.c requires a ref_clk and this is for it. > The driver will get "ref_clk" rate and check it by ufs_ref_clk_freqs[]. > > > > + > > > pmu_a55 { > > > compatible = "arm,cortex-a55-pmu"; > > > interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; > > > @@ -258,6 +265,18 @@ i2c5: i2c@e66e0000 { > > > status = "disabled"; > > > }; > > > > > > + ufs: ufs@e6860000 { > > > + compatible = "renesas,r8a779f0-ufs"; > > > + reg = <0 0xe6860000 0 0x100>; > > > + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; > > > > The R-Car S4-8 interrupt mapping spreadsheet lists two interrupts. > > Oops. I'll add it. I asked the hardware team about the listed two interrupts. Finally, I got feedback from them today. We can not use the one of interrupts. So, the spreadsheet will be revised in the future. So, we don't need to change this interrupts property. Best regards, Yoshihiro Shimoda > > > + clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>; > > > + clock-names = "fck", "ref_clk"; > > > + freq-table-hz = <200000000 200000000>, <38400000 38400000>; > > > + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; > > > + resets = <&cpg 1514>; > > > + status = "disabled"; > > > + }; > > > + > > > scif3: serial@e6c50000 { > > > compatible = "renesas,scif-r8a779f0", > > > "renesas,rcar-gen4-scif", "renesas,scif"; > > > > The rest LGTM, so with the above resolved: > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Thanks! > > Best regards, > Yoshihiro Shimoda
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index b0241aa29fc8..9639b50fb62b 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -40,6 +40,13 @@ extalr_clk: extalr { clock-frequency = <0>; }; + ufs30_clk: ufs30-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + pmu_a55 { compatible = "arm,cortex-a55-pmu"; interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; @@ -258,6 +265,18 @@ i2c5: i2c@e66e0000 { status = "disabled"; }; + ufs: ufs@e6860000 { + compatible = "renesas,r8a779f0-ufs"; + reg = <0 0xe6860000 0 0x100>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>; + clock-names = "fck", "ref_clk"; + freq-table-hz = <200000000 200000000>, <38400000 38400000>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1514>; + status = "disabled"; + }; + scif3: serial@e6c50000 { compatible = "renesas,scif-r8a779f0", "renesas,rcar-gen4-scif", "renesas,scif";
Add UFS node for R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)