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[v4,0/7] Renesas RZ/G2L IRQC support

Message ID 20220518192924.20948-1-prabhakar.mahadev-lad.rj@bp.renesas.com
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Series Renesas RZ/G2L IRQC support | expand

Message

Prabhakar Mahadev Lad May 18, 2022, 7:29 p.m. UTC
Hi All,

The RZ/G2L Interrupt Controller is a front-end for the GIC found on
Renesas RZ/G2L SoC's with below pins:
- IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI
  interrupts
- GPIO pins used as external interrupt input pins out of GPIOINT0-122 a
  maximum of only 32 can be mapped to 32 GIC SPI interrupts,
- NMI edge select.

                                                             _____________
                                                             |    GIC     |
                                                             |  ________  |
                                      ____________           | |        | |
NMI --------------------------------->|          |  SPI0-479 | | GIC-600| |
             _______                  |          |------------>|        | |
             |      |                 |          |  PPI16-31 | |        | |
             |      | IRQ0-IRQ7       |   IRQC   |------------>|        | |
P0_P48_4 --->| GPIO |---------------->|          |           | |________| |
             |      |GPIOINT0-122     |          |           |            |
             |      |---------------->| TINT0-31 |           |            |
             |______|                 |__________|           |____________|

The proposed patches add hierarchical IRQ domain, one in IRQC driver and
another in pinctrl driver. Upon interrupt requests map the interrupt to
GIC. Out of GPIOINT0-122 only 32 can be mapped to GIC SPI, this mapping is
handled by the pinctrl and IRQC driver.

Cheers,
Prabhakar

Changes for v3->v4:
* Updated description for interrupts-cells property in patch #1
* Dropped the patch which overriding free callback in gpiolib
* Used devm helpers in patch#2
* Patch #4, #5 and #6 are newly added
* In patch #7 dropped using gpio offset as hwirq
* Implemented immutable GPIO in patch #7
* Implemented child_offset_to_irq() callback in patch #7

Changes for v2->v3:
* Updated description for interrupts-cells property in patch #1
* Included RB tag from Geert for binding patch
* Fixed review comments pointed by Geert, Biju and Sergei.

Changes for v1->v2:
* Included RB tag from Rob
* Fixed review comments pointed by Geert
* included GPIO driver changes

Changes for RFCV4 -> V1:
* Used unevaluatedProperties.
* Altered the sequence of reg property
* Set the parent type
* Used raw_spin_lock() instead of raw_spin_lock_irqsave()
* Simplified parsing IRQ map.
* Will send the GPIO and pinctrl changes as part of separate series

Changes for RFC v4:
* Used locking while RMW
* Now using interrupts property instead of interrupt-map
* Patch series depends on [0]
* Updated binding doc
* Fixed comments pointed by Andy

[0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
20220316200633.28974-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/

Changes for RFC v3:
-> Re-structured the driver as a hierarchical irq domain instead of chained
-> made use of IRQCHIP_* macros
-> dropped locking
-> Added support for IRQ0-7 interrupts
-> Introduced 2 new patches for GPIOLIB
-> Switched to using GPIOLIB for irqdomains in pinctrl

RFC v2: https://patchwork.kernel.org/project/linux-renesas-soc/cover/
20210921193028.13099-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/

RFC v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/
20210803175109.1729-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/

Lad Prabhakar (7):
  dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt
    Controller
  irqchip: Add RZ/G2L IA55 Interrupt Controller driver
  gpio: gpiolib: Add ngirq member to struct gpio_irq_chip
  gpio: gpiolib: Dont assume child_offset_to_irq callback always
    succeeds
  gpio: gpiolib: Add a check to validate GPIO hwirq
  dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the properties
    to handle GPIO IRQ
  pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO
    interrupt

 .../renesas,rzg2l-irqc.yaml                   | 133 ++++++
 .../pinctrl/renesas,rzg2l-pinctrl.yaml        |  16 +
 drivers/gpio/gpio-tegra186.c                  |  14 +-
 drivers/gpio/gpiolib.c                        |  38 +-
 drivers/irqchip/Kconfig                       |   8 +
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-renesas-rzg2l.c           | 425 ++++++++++++++++++
 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c      |   7 +-
 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c       |   7 +-
 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c      |   7 +-
 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c       |   7 +-
 drivers/pinctrl/renesas/pinctrl-rzg2l.c       | 221 +++++++++
 include/linux/gpio/driver.h                   |  17 +-
 13 files changed, 880 insertions(+), 21 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
 create mode 100644 drivers/irqchip/irq-renesas-rzg2l.c

Comments

Andy Shevchenko May 18, 2022, 9:09 p.m. UTC | #1
On Wed, May 18, 2022 at 9:29 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
>
> Hi All,
>
> The RZ/G2L Interrupt Controller is a front-end for the GIC found on
> Renesas RZ/G2L SoC's with below pins:
> - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI
>   interrupts
> - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a
>   maximum of only 32 can be mapped to 32 GIC SPI interrupts,
> - NMI edge select.
>
>                                                              _____________
>                                                              |    GIC     |
>                                                              |  ________  |
>                                       ____________           | |        | |
> NMI --------------------------------->|          |  SPI0-479 | | GIC-600| |
>              _______                  |          |------------>|        | |
>              |      |                 |          |  PPI16-31 | |        | |
>              |      | IRQ0-IRQ7       |   IRQC   |------------>|        | |
> P0_P48_4 --->| GPIO |---------------->|          |           | |________| |
>              |      |GPIOINT0-122     |          |           |            |
>              |      |---------------->| TINT0-31 |           |            |
>              |______|                 |__________|           |____________|
>
> The proposed patches add hierarchical IRQ domain, one in IRQC driver and
> another in pinctrl driver. Upon interrupt requests map the interrupt to
> GIC. Out of GPIOINT0-122 only 32 can be mapped to GIC SPI, this mapping is
> handled by the pinctrl and IRQC driver.

Where is the explanation on why valid_mask can't be used instead?
Lad, Prabhakar May 19, 2022, 4:07 a.m. UTC | #2
On Wed, May 18, 2022 at 10:10 PM Andy Shevchenko
<andy.shevchenko@gmail.com> wrote:
>
> On Wed, May 18, 2022 at 9:29 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> >
> > Hi All,
> >
> > The RZ/G2L Interrupt Controller is a front-end for the GIC found on
> > Renesas RZ/G2L SoC's with below pins:
> > - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI
> >   interrupts
> > - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a
> >   maximum of only 32 can be mapped to 32 GIC SPI interrupts,
> > - NMI edge select.
> >
> >                                                              _____________
> >                                                              |    GIC     |
> >                                                              |  ________  |
> >                                       ____________           | |        | |
> > NMI --------------------------------->|          |  SPI0-479 | | GIC-600| |
> >              _______                  |          |------------>|        | |
> >              |      |                 |          |  PPI16-31 | |        | |
> >              |      | IRQ0-IRQ7       |   IRQC   |------------>|        | |
> > P0_P48_4 --->| GPIO |---------------->|          |           | |________| |
> >              |      |GPIOINT0-122     |          |           |            |
> >              |      |---------------->| TINT0-31 |           |            |
> >              |______|                 |__________|           |____________|
> >
> > The proposed patches add hierarchical IRQ domain, one in IRQC driver and
> > another in pinctrl driver. Upon interrupt requests map the interrupt to
> > GIC. Out of GPIOINT0-122 only 32 can be mapped to GIC SPI, this mapping is
> > handled by the pinctrl and IRQC driver.
>
> Where is the explanation on why valid_mask can't be used instead?
>
The .valid_mask option is one time setting but what I need is
something dynamic i.e. out of 392 GPIO pins any 32 can be used as an
interrupt pin. Also with this patch we also save on memory here [0].

[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/kernel/irq/irqdomain.c?h=next-20220518#n153

Cheers,
Prabhakar
>
> --
> With Best Regards,
> Andy Shevchenko
Biju Das May 19, 2022, 6:58 a.m. UTC | #3
Hi Prabhakar,

> Subject: Re: [PATCH v4 0/7] Renesas RZ/G2L IRQC support
> 
> On Wed, May 18, 2022 at 10:10 PM Andy Shevchenko
> <andy.shevchenko@gmail.com> wrote:
> >
> > On Wed, May 18, 2022 at 9:29 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > >
> > > Hi All,
> > >
> > > The RZ/G2L Interrupt Controller is a front-end for the GIC found on
> > > Renesas RZ/G2L SoC's with below pins:
> > > - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI
> > >   interrupts
> > > - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a
> > >   maximum of only 32 can be mapped to 32 GIC SPI interrupts,
> > > - NMI edge select.
> > >
> > >
> _____________
> > >                                                              |    GIC
> |
> > >                                                              |
> ________  |
> > >                                       ____________           | |
> | |
> > > NMI --------------------------------->|          |  SPI0-479 | | GIC-
> 600| |
> > >              _______                  |          |------------>|
> | |
> > >              |      |                 |          |  PPI16-31 | |
> | |
> > >              |      | IRQ0-IRQ7       |   IRQC   |------------>|
> | |
> > > P0_P48_4 --->| GPIO |---------------->|          |           |
> |________| |
> > >              |      |GPIOINT0-122     |          |           |
> |
> > >              |      |---------------->| TINT0-31 |           |
> |
> > >              |______|                 |__________|
> |____________|
> > >
> > > The proposed patches add hierarchical IRQ domain, one in IRQC driver
> > > and another in pinctrl driver. Upon interrupt requests map the
> > > interrupt to GIC. Out of GPIOINT0-122 only 32 can be mapped to GIC
> > > SPI, this mapping is handled by the pinctrl and IRQC driver.
> >
> > Where is the explanation on why valid_mask can't be used instead?
> >
> The .valid_mask option is one time setting 

One question, if it is one time setting, Is it possible to use .valid mask to invalidate 
invalid gpio lines?(ie, currently gpio range is 392, but there is only 123 GPIOs
present in the SoC, not sure this call back can be used to invalidate the non-supported GPIOS??).

Cheers,
Biju



but what I need is something
> dynamic i.e. out of 392 GPIO pins any 32 can be used as an interrupt pin.
> Also with this patch we also save on memory here [0].
,
> > Andy Shevchenko
Andy Shevchenko May 19, 2022, 10:07 a.m. UTC | #4
On Thu, May 19, 2022 at 6:07 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Wed, May 18, 2022 at 10:10 PM Andy Shevchenko
> <andy.shevchenko@gmail.com> wrote:
> > On Wed, May 18, 2022 at 9:29 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:

...

> > > GIC. Out of GPIOINT0-122 only 32 can be mapped to GIC SPI, this mapping is
> > > handled by the pinctrl and IRQC driver.
> >
> > Where is the explanation on why valid_mask can't be used instead?
> >
> The .valid_mask option is one time setting but what I need is
> something dynamic i.e. out of 392 GPIO pins any 32 can be used as an
> interrupt pin. Also with this patch we also save on memory here [0].

Which internal APIs are bound to valid_mask not to be updated?
Lad, Prabhakar May 23, 2022, 5:28 p.m. UTC | #5
Hi Biju,

On Thu, May 19, 2022 at 7:58 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > Subject: Re: [PATCH v4 0/7] Renesas RZ/G2L IRQC support
> >
> > On Wed, May 18, 2022 at 10:10 PM Andy Shevchenko
> > <andy.shevchenko@gmail.com> wrote:
> > >
> > > On Wed, May 18, 2022 at 9:29 PM Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > >
> > > > Hi All,
> > > >
> > > > The RZ/G2L Interrupt Controller is a front-end for the GIC found on
> > > > Renesas RZ/G2L SoC's with below pins:
> > > > - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI
> > > >   interrupts
> > > > - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a
> > > >   maximum of only 32 can be mapped to 32 GIC SPI interrupts,
> > > > - NMI edge select.
> > > >
> > > >
> > _____________
> > > >                                                              |    GIC
> > |
> > > >                                                              |
> > ________  |
> > > >                                       ____________           | |
> > | |
> > > > NMI --------------------------------->|          |  SPI0-479 | | GIC-
> > 600| |
> > > >              _______                  |          |------------>|
> > | |
> > > >              |      |                 |          |  PPI16-31 | |
> > | |
> > > >              |      | IRQ0-IRQ7       |   IRQC   |------------>|
> > | |
> > > > P0_P48_4 --->| GPIO |---------------->|          |           |
> > |________| |
> > > >              |      |GPIOINT0-122     |          |           |
> > |
> > > >              |      |---------------->| TINT0-31 |           |
> > |
> > > >              |______|                 |__________|
> > |____________|
> > > >
> > > > The proposed patches add hierarchical IRQ domain, one in IRQC driver
> > > > and another in pinctrl driver. Upon interrupt requests map the
> > > > interrupt to GIC. Out of GPIOINT0-122 only 32 can be mapped to GIC
> > > > SPI, this mapping is handled by the pinctrl and IRQC driver.
> > >
> > > Where is the explanation on why valid_mask can't be used instead?
> > >
> > The .valid_mask option is one time setting
>
> One question, if it is one time setting, Is it possible to use .valid mask to invalidate
> invalid gpio lines?(ie, currently gpio range is 392, but there is only 123 GPIOs
> present in the SoC, not sure this call back can be used to invalidate the non-supported GPIOS??).
>
Yes can be added, I will include it in the next version.

Cheers,
Prabhakar