[02/47] target/arm: Use tcg_constant in gen_mte_check*

Message ID	20220426163043.100432-3-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH 02/47] target/arm: Use tcg_constant in gen_mte_check* Date: Tue, 26 Apr 2022 09:29:58 -0700 Message-Id: <20220426163043.100432-3-richard.henderson@linaro.org> In-Reply-To: <20220426163043.100432-1-richard.henderson@linaro.org> References: <20220426163043.100432-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: Use tcg_constant \| expand [00/47] target/arm: Use tcg_constant [01/47] target/arm: Use tcg_constant in gen_probe_access [02/47] target/arm: Use tcg_constant in gen_mte_check* [03/47] target/arm: Use tcg_constant in gen_exception* [04/47] target/arm: Use tcg_constant in gen_adc_CC [05/47] target/arm: Use tcg_constant in handle_msr_i [06/47] target/arm: Use tcg_constant in handle_sys [07/47] target/arm: Use tcg_constant in disas_exc [08/47] target/arm: Use tcg_constant in gen_compare_and_swap_pair [09/47] target/arm: Use tcg_constant in disas_ld_lit [10/47] target/arm: Use tcg_constant in disas_ldst_* [11/47] target/arm: Use tcg_constant in disas_add_sum_imm* [12/47] target/arm: Use tcg_constant in disas_movw_imm [13/47] target/arm: Use tcg_constant in shift_reg_imm [14/47] target/arm: Use tcg_constant in disas_cond_select [15/47] target/arm: Use tcg_constant in handle_{rev16,crc32} [16/47] target/arm: Use tcg_constant in disas_data_proc_2src [17/47] target/arm: Use tcg_constant in disas_fp* [18/47] target/arm: Use tcg_constant in simd shift expanders [19/47] target/arm: Use tcg_constant in simd fp/int conversion [20/47] target/arm: Use tcg_constant in 2misc expanders [21/47] target/arm: Use tcg_constant in balance of translate-a64.c [22/47] target/arm: Use tcg_constant for aa32 exceptions [23/47] target/arm: Use tcg_constant for disas_iwmmxt_insn [24/47] target/arm: Use tcg_constant for gen_{msr,mrs} [25/47] target/arm: Use tcg_constant for vector shift expanders [26/47] target/arm: Use tcg_constant for do_coproc_insn [27/47] target/arm: Use tcg_constant for gen_srs [28/47] target/arm: Use tcg_constant for op_s_{rri,rxi}_rot [29/47] target/arm: Use tcg_constant for MOVW, UMAAL, CRC32 [30/47] target/arm: Use tcg_constant for v7m MRS, MSR [31/47] target/arm: Use tcg_constant for TT, SAT, SMMLA [32/47] target/arm: Use tcg_constant in LDM, STM [33/47] target/arm: Use tcg_constant in CLRM, DLS, WLS, LE [34/47] target/arm: Use tcg_constant in trans_CPS_v7m [35/47] target/arm: Use tcg_constant in trans_CSEL [36/47] target/arm: Use tcg_constant for trans_INDEX_* [37/47] target/arm: Use tcg_constant in SINCDEC, INCDEC [38/47] target/arm: Use tcg_constant in FCPY, CPY [39/47] target/arm: Use tcg_constant in {incr, wrap}_last_active [40/47] target/arm: Use tcg_constant in do_clast_scalar [41/47] target/arm: Use tcg_constant in WHILE [42/47] target/arm: Use tcg_constant in LD1, ST1 [43/47] target/arm: Use tcg_constant in SUBR [44/47] target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm [45/47] target/arm: Use tcg_constant for predicate descriptors [46/47] target/arm: Use tcg_constant for do_brk{2,3} [47/47] target/arm: Use tcg_constant for vector descriptor

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20220426163043.100432-3-richard.henderson@linaro.org

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Superseded

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 02/47] target/arm: Use tcg_constant in gen_mte_check*
Date: Tue, 26 Apr 2022 09:29:58 -0700
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Series

target/arm: Use tcg_constant | expand

Comments

Peter Maydell April 28, 2022, 9:36 a.m. UTC | #1

On Tue, 26 Apr 2022 at 17:32, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/translate-a64.c | 10 ++--------
>  1 file changed, 2 insertions(+), 8 deletions(-)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c6ab0433af..7b5bfb0889 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -258,7 +258,6 @@  static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,
                                       int core_idx)
 {
     if (tag_checked && s->mte_active[is_unpriv]) {
-        TCGv_i32 tcg_desc;
         TCGv_i64 ret;
         int desc = 0;
 
@@ -267,11 +266,9 @@  static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,
         desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
         desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
         desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << log2_size) - 1);
-        tcg_desc = tcg_const_i32(desc);
 
         ret = new_tmp_a64(s);
-        gen_helper_mte_check(ret, cpu_env, tcg_desc, addr);
-        tcg_temp_free_i32(tcg_desc);
+        gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr);
 
         return ret;
     }
@@ -292,7 +289,6 @@  TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
                         bool tag_checked, int size)
 {
     if (tag_checked && s->mte_active[0]) {
-        TCGv_i32 tcg_desc;
         TCGv_i64 ret;
         int desc = 0;
 
@@ -301,11 +297,9 @@  TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
         desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
         desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
         desc = FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1);
-        tcg_desc = tcg_const_i32(desc);
 
         ret = new_tmp_a64(s);
-        gen_helper_mte_check(ret, cpu_env, tcg_desc, addr);
-        tcg_temp_free_i32(tcg_desc);
+        gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr);
 
         return ret;
     }

[02/47] target/arm: Use tcg_constant in gen_mte_check*

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