diff mbox series

[v3,07/60] target/arm: Extend store_cpu_offset to take field size

Message ID 20220417174426.711829-8-richard.henderson@linaro.org
State Superseded
Headers show
Series target/arm: Cleanups, new features, new cpus | expand

Commit Message

Richard Henderson April 17, 2022, 5:43 p.m. UTC 
Currently we assume all fields are 32-bit.
Prepare for fields of a single byte, using sizeof.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate-a32.h | 13 +++++--------
 target/arm/translate.c     | 21 ++++++++++++++++++++-
 2 files changed, 25 insertions(+), 9 deletions(-)

Comments

Peter Maydell April 21, 2022, 4:15 p.m. UTC | #1 
On Sun, 17 Apr 2022 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Currently we assume all fields are 32-bit.
> Prepare for fields of a single byte, using sizeof.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/translate-a32.h | 13 +++++--------
>  target/arm/translate.c     | 21 ++++++++++++++++++++-
>  2 files changed, 25 insertions(+), 9 deletions(-)
>
> diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h
> index 5be4b9b834..f593740a88 100644
> --- a/target/arm/translate-a32.h
> +++ b/target/arm/translate-a32.h
> @@ -61,17 +61,14 @@ static inline TCGv_i32 load_cpu_offset(int offset)
>
>  #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
>
> -static inline void store_cpu_offset(TCGv_i32 var, int offset)
> -{
> -    tcg_gen_st_i32(var, cpu_env, offset);
> -    tcg_temp_free_i32(var);
> -}
> +void store_cpu_offset(TCGv_i32 var, int offset, int size);
>
> -#define store_cpu_field(var, name) \
> -    store_cpu_offset(var, offsetof(CPUARMState, name))
> +#define store_cpu_field(var, name)                              \
> +    store_cpu_offset(var, offsetof(CPUARMState, name),          \
> +                     sizeof(((CPUARMState *)NULL)->name))

compiler.h defines sizeof_field, so you can write
  sizeof_field(CPUARMState, name)
here.

Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM
Alex Bennée April 22, 2022, 1:58 p.m. UTC | #2 
Richard Henderson <richard.henderson@linaro.org> writes:

> Currently we assume all fields are 32-bit.
> Prepare for fields of a single byte, using sizeof.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
diff mbox series

Patch

diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h
index 5be4b9b834..f593740a88 100644
--- a/target/arm/translate-a32.h
+++ b/target/arm/translate-a32.h
@@ -61,17 +61,14 @@  static inline TCGv_i32 load_cpu_offset(int offset)
 
 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
 
-static inline void store_cpu_offset(TCGv_i32 var, int offset)
-{
-    tcg_gen_st_i32(var, cpu_env, offset);
-    tcg_temp_free_i32(var);
-}
+void store_cpu_offset(TCGv_i32 var, int offset, int size);
 
-#define store_cpu_field(var, name) \
-    store_cpu_offset(var, offsetof(CPUARMState, name))
+#define store_cpu_field(var, name)                              \
+    store_cpu_offset(var, offsetof(CPUARMState, name),          \
+                     sizeof(((CPUARMState *)NULL)->name))
 
 #define store_cpu_field_constant(val, name) \
-    tcg_gen_st_i32(tcg_constant_i32(val), cpu_env, offsetof(CPUARMState, name))
+    store_cpu_field(tcg_constant_i32(val), name)
 
 /* Create a new temporary and set it to the value of a CPU register.  */
 static inline TCGv_i32 load_reg(DisasContext *s, int reg)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 480e58f49e..c745b7fc91 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -180,6 +180,25 @@  typedef enum ISSInfo {
     ISSIs16Bit = (1 << 8),
 } ISSInfo;
 
+/*
+ * Store var into env + offset to a member with size bytes.
+ * Free var after use.
+ */
+void store_cpu_offset(TCGv_i32 var, int offset, int size)
+{
+    switch (size) {
+    case 1:
+        tcg_gen_st8_i32(var, cpu_env, offset);
+        break;
+    case 4:
+        tcg_gen_st_i32(var, cpu_env, offset);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+    tcg_temp_free_i32(var);
+}
+
 /* Save the syndrome information for a Data Abort */
 static void disas_set_da_iss(DisasContext *s, MemOp memop, ISSInfo issinfo)
 {
@@ -4852,7 +4871,7 @@  static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
                     tcg_temp_free_i32(tmp);
                 } else {
                     TCGv_i32 tmp = load_reg(s, rt);
-                    store_cpu_offset(tmp, ri->fieldoffset);
+                    store_cpu_offset(tmp, ri->fieldoffset, 4);
                 }
             }
         }