| Message ID | 20220411091157.1965623-1-jerry.huang@nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] arm64: dts: fsl-ls1028a: add dspi2 support | expand |
On Mon, Apr 11, 2022 at 05:11:57PM +0800, Changming Huang wrote: > Enable MikroBUS SPI port. > > Signed-off-by: Jianchao Wang <jianchao.wang@nxp.com> > Signed-off-by: Changming Huang <jerry.huang@nxp.com> > --- > arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 13 +++++++++++++ "arm64: dts: fsl-ls1028a-rdb: ..." to make it clear this is a board rather than SoC change. > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts > index 68c31cb8eead..6d0508d5abd0 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts > @@ -117,6 +117,19 @@ &duart1 { > status = "okay"; > }; > > +&dspi2 { > + bus-num = <2>; > + status = "okay"; > + > + mikrobus@0 { > + compatible = "semtech,sx1301"; Where is the bindings for this? Shawn > + reg = <0>; > + spi-max-frequency = <2000000>; > + fsl,spi-cs-sck-delay = <1000000>; > + fsl,spi-sck-cs-delay = <50>; > + }; > +}; > + > &enetc_mdio_pf3 { > sgmii_phy0: ethernet-phy@2 { > reg = <0x2>; > -- > 2.25.1 >
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 68c31cb8eead..6d0508d5abd0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -117,6 +117,19 @@ &duart1 { status = "okay"; }; +&dspi2 { + bus-num = <2>; + status = "okay"; + + mikrobus@0 { + compatible = "semtech,sx1301"; + reg = <0>; + spi-max-frequency = <2000000>; + fsl,spi-cs-sck-delay = <1000000>; + fsl,spi-sck-cs-delay = <50>; + }; +}; + &enetc_mdio_pf3 { sgmii_phy0: ethernet-phy@2 { reg = <0x2>;