| Message ID | 20220303202341.2232284-4-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm gicv3: minor bug fixes, ITS trace events | expand |
On 3/3/22 10:23, Peter Maydell wrote: > The GICv3 has some registers that support byte accesses, and some > that support 8-byte accesses. Our TCG implementation implements all > of this, switching on the 'size' argument and handling the registers > that must support reads of that size while logging an error for > attempted accesses to registers that do not support that size access. > However we forgot to tell the core memory subsystem about this by > specifying the .impl and .valid fields in the MemoryRegionOps struct, > so the core was happily simulating 8 byte accesses by combining two 4 > byte accesses. This doesn't have much guest-visible effect, since > there aren't many 8 byte registers and they all support being written > in two 4 byte parts. > > Set the .impl and .valid fields to say that all sizes from 1 to 8 > bytes are both valid and implemented by the device. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 6d3c8ee231c..0b8f79a1227 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -369,11 +369,19 @@ static const MemoryRegionOps gic_ops[] = { .read_with_attrs = gicv3_dist_read, .write_with_attrs = gicv3_dist_write, .endianness = DEVICE_NATIVE_ENDIAN, + .valid.min_access_size = 1, + .valid.max_access_size = 8, + .impl.min_access_size = 1, + .impl.max_access_size = 8, }, { .read_with_attrs = gicv3_redist_read, .write_with_attrs = gicv3_redist_write, .endianness = DEVICE_NATIVE_ENDIAN, + .valid.min_access_size = 1, + .valid.max_access_size = 8, + .impl.min_access_size = 1, + .impl.max_access_size = 8, } };
The GICv3 has some registers that support byte accesses, and some that support 8-byte accesses. Our TCG implementation implements all of this, switching on the 'size' argument and handling the registers that must support reads of that size while logging an error for attempted accesses to registers that do not support that size access. However we forgot to tell the core memory subsystem about this by specifying the .impl and .valid fields in the MemoryRegionOps struct, so the core was happily simulating 8 byte accesses by combining two 4 byte accesses. This doesn't have much guest-visible effect, since there aren't many 8 byte registers and they all support being written in two 4 byte parts. Set the .impl and .valid fields to say that all sizes from 1 to 8 bytes are both valid and implemented by the device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/intc/arm_gicv3.c | 8 ++++++++ 1 file changed, 8 insertions(+)