Message ID | 20220127091808.1043392-10-miquel.raynal@bootlin.com |
---|---|
State | Accepted |
Commit | 5fd6739e0df7e320bcac103dfb95fe75941fea17 |
Headers | show |
Series | [v10,01/13] spi: spi-mem: Introduce a capability structure | expand |
On Thu, 2022-01-27 at 09:18:04 UTC, Miquel Raynal wrote: > By working with external hardware ECC engines, we figured out that > Under certain circumstances, it is needed for the SPI controller to > check INT_TX_EMPTY and INT_RX_NOT_EMPTY in both receive and transmit > path (not only in the receive path). The delay penalty being > negligible, move this code in the common path. > > Fixes: b942d80b0a39 ("spi: Add MXIC controller driver") > Cc: stable@vger.kernel.org > Suggested-by: Mason Yang <masonccyang@mxic.com.tw> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > Reviewed-by: Zhengxun Li <zhengxunli@mxic.com.tw> > Reviewed-by: Mark Brown <broonie@kernel.org> > Link: https://lore.kernel.org/linux-mtd/20220104083631.40776-10-miquel.raynal@bootlin.com Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git spi-mem-ecc. Miquel
diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 6bec0a7c77d3..22a82f5f74b5 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -304,25 +304,21 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, writel(data, mxic->regs + TXD(nbytes % 4)); + ret = readl_poll_timeout(mxic->regs + INT_STS, sts, + sts & INT_TX_EMPTY, 0, USEC_PER_SEC); + if (ret) + return ret; + + ret = readl_poll_timeout(mxic->regs + INT_STS, sts, + sts & INT_RX_NOT_EMPTY, 0, + USEC_PER_SEC); + if (ret) + return ret; + + data = readl(mxic->regs + RXD); if (rxbuf) { - ret = readl_poll_timeout(mxic->regs + INT_STS, sts, - sts & INT_TX_EMPTY, 0, - USEC_PER_SEC); - if (ret) - return ret; - - ret = readl_poll_timeout(mxic->regs + INT_STS, sts, - sts & INT_RX_NOT_EMPTY, 0, - USEC_PER_SEC); - if (ret) - return ret; - - data = readl(mxic->regs + RXD); data >>= (8 * (4 - nbytes)); memcpy(rxbuf + pos, &data, nbytes); - WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY); - } else { - readl(mxic->regs + RXD); } WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);