diff mbox series

[v8,3/3] usb: dwc3: xilinx: Add ULPI PHY reset handling

Message ID 20220126234017.3619108-4-robert.hancock@calian.com
State New
Headers show
Series Xilinx ZynqMP USB fixes | expand

Commit Message

Robert Hancock Jan. 26, 2022, 11:40 p.m. UTC 
Hook up an optional GPIO-based reset for the connected USB ULPI PHY
device. This is typically already done by the first-stage boot loader,
however it can be more robust to ensure this reset is done prior to
loading the driver in Linux.

Based on a patch "usb: dwc3: xilinx: Add gpio-reset support" in the
Xilinx kernel tree by Piyush Mehta <piyush.mehta@xilinx.com>.

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
 drivers/usb/dwc3/dwc3-xilinx.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

Comments

Sean Anderson Jan. 27, 2022, 8:10 p.m. UTC | #1 
Hi Rob,

On 1/26/22 6:40 PM, Robert Hancock wrote:
> Hook up an optional GPIO-based reset for the connected USB ULPI PHY
> device. This is typically already done by the first-stage boot loader,
> however it can be more robust to ensure this reset is done prior to
> loading the driver in Linux.
> 
> Based on a patch "usb: dwc3: xilinx: Add gpio-reset support" in the
> Xilinx kernel tree by Piyush Mehta <piyush.mehta@xilinx.com>.
> 
> Signed-off-by: Robert Hancock <robert.hancock@calian.com>
> ---
>  drivers/usb/dwc3/dwc3-xilinx.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c
> index a6f3a9b38789..1ee6011ada44 100644
> --- a/drivers/usb/dwc3/dwc3-xilinx.c
> +++ b/drivers/usb/dwc3/dwc3-xilinx.c
> @@ -11,6 +11,7 @@
>  #include <linux/slab.h>
>  #include <linux/clk.h>
>  #include <linux/of.h>
> +#include <linux/gpio/consumer.h>
>  #include <linux/platform_device.h>
>  #include <linux/dma-mapping.h>
>  #include <linux/of_platform.h>
> @@ -101,6 +102,7 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
>  	struct phy		*usb3_phy;
>  	int			ret = 0;
>  	u32			reg;
> +	struct gpio_desc        *reset_gpio;
>  
>  	usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
>  	if (IS_ERR(usb3_phy)) {
> @@ -110,6 +112,14 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
>  		goto err;
>  	}
>  
> +	reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
> +	if (IS_ERR(reset_gpio)) {
> +		ret = PTR_ERR(reset_gpio);
> +		dev_err_probe(dev, ret,
> +			      "Failed to get reset gpio\n");
> +		goto err;
> +	}
> +
>  	/*
>  	 * The following core resets are not required unless a USB3 PHY
>  	 * is used, and the subsequent register settings are not required
> @@ -201,6 +211,15 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
>  	}
>  
>  skip_usb3_phy:
> +	/* ulpi reset via gpio-modepin or gpio-framework driver */
> +	if (reset_gpio) {
> +		/* Toggle ulpi to reset the phy. */
> +		gpiod_set_value(reset_gpio, 0);
> +		usleep_range(5000, 10000); /* delay */
> +		gpiod_set_value(reset_gpio, 1);
> +		usleep_range(5000, 10000); /* delay */
> +	}
> +
>  	/*
>  	 * This routes the USB DMA traffic to go through FPD path instead
>  	 * of reaching DDR directly. This traffic routing is needed to
> 

Do we need to have this in dwc3? Why not just use the usb-nop-xceiv driver (aka usb_phy_generic)?

--Sean
Robert Hancock Jan. 27, 2022, 9:45 p.m. UTC | #2 
On Thu, 2022-01-27 at 15:10 -0500, Sean Anderson wrote:
> Hi Rob,
> 
> On 1/26/22 6:40 PM, Robert Hancock wrote:
> > Hook up an optional GPIO-based reset for the connected USB ULPI PHY
> > device. This is typically already done by the first-stage boot loader,
> > however it can be more robust to ensure this reset is done prior to
> > loading the driver in Linux.
> > 
> > Based on a patch "usb: dwc3: xilinx: Add gpio-reset support" in the
> > Xilinx kernel tree by Piyush Mehta <piyush.mehta@xilinx.com>.
> > 
> > Signed-off-by: Robert Hancock <robert.hancock@calian.com>
> > ---
> >  drivers/usb/dwc3/dwc3-xilinx.c | 19 +++++++++++++++++++
> >  1 file changed, 19 insertions(+)
> > 
> > diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-
> > xilinx.c
> > index a6f3a9b38789..1ee6011ada44 100644
> > --- a/drivers/usb/dwc3/dwc3-xilinx.c
> > +++ b/drivers/usb/dwc3/dwc3-xilinx.c
> > @@ -11,6 +11,7 @@
> >  #include <linux/slab.h>
> >  #include <linux/clk.h>
> >  #include <linux/of.h>
> > +#include <linux/gpio/consumer.h>
> >  #include <linux/platform_device.h>
> >  #include <linux/dma-mapping.h>
> >  #include <linux/of_platform.h>
> > @@ -101,6 +102,7 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx
> > *priv_data)
> >  	struct phy		*usb3_phy;
> >  	int			ret = 0;
> >  	u32			reg;
> > +	struct gpio_desc        *reset_gpio;
> >  
> >  	usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
> >  	if (IS_ERR(usb3_phy)) {
> > @@ -110,6 +112,14 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx
> > *priv_data)
> >  		goto err;
> >  	}
> >  
> > +	reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
> > +	if (IS_ERR(reset_gpio)) {
> > +		ret = PTR_ERR(reset_gpio);
> > +		dev_err_probe(dev, ret,
> > +			      "Failed to get reset gpio\n");
> > +		goto err;
> > +	}
> > +
> >  	/*
> >  	 * The following core resets are not required unless a USB3 PHY
> >  	 * is used, and the subsequent register settings are not required
> > @@ -201,6 +211,15 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx
> > *priv_data)
> >  	}
> >  
> >  skip_usb3_phy:
> > +	/* ulpi reset via gpio-modepin or gpio-framework driver */
> > +	if (reset_gpio) {
> > +		/* Toggle ulpi to reset the phy. */
> > +		gpiod_set_value(reset_gpio, 0);
> > +		usleep_range(5000, 10000); /* delay */
> > +		gpiod_set_value(reset_gpio, 1);
> > +		usleep_range(5000, 10000); /* delay */
> > +	}
> > +
> >  	/*
> >  	 * This routes the USB DMA traffic to go through FPD path instead
> >  	 * of reaching DDR directly. This traffic routing is needed to
> > 
> 
> Do we need to have this in dwc3? Why not just use the usb-nop-xceiv driver
> (aka usb_phy_generic)?

I hadn't noticed that option. Just tried it out and it seems like it does
what's needed. So patches 2 and 3 can be dispensed with. Patch 1 is still
needed however, I may resubmit that as a standalone patch..

> 
> --Sean
diff mbox series

Patch

diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c
index a6f3a9b38789..1ee6011ada44 100644
--- a/drivers/usb/dwc3/dwc3-xilinx.c
+++ b/drivers/usb/dwc3/dwc3-xilinx.c
@@ -11,6 +11,7 @@ 
 #include <linux/slab.h>
 #include <linux/clk.h>
 #include <linux/of.h>
+#include <linux/gpio/consumer.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/of_platform.h>
@@ -101,6 +102,7 @@  static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
 	struct phy		*usb3_phy;
 	int			ret = 0;
 	u32			reg;
+	struct gpio_desc        *reset_gpio;
 
 	usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
 	if (IS_ERR(usb3_phy)) {
@@ -110,6 +112,14 @@  static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
 		goto err;
 	}
 
+	reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
+	if (IS_ERR(reset_gpio)) {
+		ret = PTR_ERR(reset_gpio);
+		dev_err_probe(dev, ret,
+			      "Failed to get reset gpio\n");
+		goto err;
+	}
+
 	/*
 	 * The following core resets are not required unless a USB3 PHY
 	 * is used, and the subsequent register settings are not required
@@ -201,6 +211,15 @@  static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
 	}
 
 skip_usb3_phy:
+	/* ulpi reset via gpio-modepin or gpio-framework driver */
+	if (reset_gpio) {
+		/* Toggle ulpi to reset the phy. */
+		gpiod_set_value(reset_gpio, 0);
+		usleep_range(5000, 10000); /* delay */
+		gpiod_set_value(reset_gpio, 1);
+		usleep_range(5000, 10000); /* delay */
+	}
+
 	/*
 	 * This routes the USB DMA traffic to go through FPD path instead
 	 * of reaching DDR directly. This traffic routing is needed to