diff mbox series

[v2,2/7] x86: Add definitions for the Intel Hardware Feedback Interface

Message ID 20211220151438.1196-3-ricardo.neri-calderon@linux.intel.com
State Superseded
Headers show
Series Thermal: Introduce the Hardware Feedback Interface for thermal and performance management | expand

Commit Message

Ricardo Neri Dec. 20, 2021, 3:14 p.m. UTC
Add the CPUID feature bit and the model-specific registers needed to
identify and configure the Intel Hardware Feedback Interface.

Cc: Andi Kleen <ak@linux.intel.com>
Cc: Aubrey Li <aubrey.li@linux.intel.com>
Cc: Len Brown <len.brown@intel.com>
Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Cc: Tim Chen <tim.c.chen@linux.intel.com>
Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com>
Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
---
Changes since v1:
  * Renamed X86_FEATURE_INTEL_HFI as X86_FEATURE_HFI. (Boris)
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 arch/x86/include/asm/msr-index.h   | 6 ++++++
 2 files changed, 7 insertions(+)

Comments

Rafael J. Wysocki Dec. 30, 2021, 6:03 p.m. UTC | #1
On Mon, Dec 20, 2021 at 4:23 PM Ricardo Neri
<ricardo.neri-calderon@linux.intel.com> wrote:
>
> Add the CPUID feature bit and the model-specific registers needed to
> identify and configure the Intel Hardware Feedback Interface.
>
> Cc: Andi Kleen <ak@linux.intel.com>
> Cc: Aubrey Li <aubrey.li@linux.intel.com>
> Cc: Len Brown <len.brown@intel.com>
> Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
> Cc: Tim Chen <tim.c.chen@linux.intel.com>
> Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com>
> Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
> ---
> Changes since v1:
>   * Renamed X86_FEATURE_INTEL_HFI as X86_FEATURE_HFI. (Boris)

It would be good to get an ACK from the x86 side for this.

> ---
>  arch/x86/include/asm/cpufeatures.h | 1 +
>  arch/x86/include/asm/msr-index.h   | 6 ++++++
>  2 files changed, 7 insertions(+)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index d5b5f2ab87a0..1a31b3ef15f0 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -327,6 +327,7 @@
>  #define X86_FEATURE_HWP_ACT_WINDOW     (14*32+ 9) /* HWP Activity Window */
>  #define X86_FEATURE_HWP_EPP            (14*32+10) /* HWP Energy Perf. Preference */
>  #define X86_FEATURE_HWP_PKG_REQ                (14*32+11) /* HWP Package Level Request */
> +#define X86_FEATURE_HFI                        (14*32+19) /* Hardware Feedback Interface */
>
>  /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
>  #define X86_FEATURE_NPT                        (15*32+ 0) /* Nested Page Table support */
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 01e2650b9585..ad958a49b2bb 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -687,12 +687,14 @@
>
>  #define PACKAGE_THERM_STATUS_PROCHOT           (1 << 0)
>  #define PACKAGE_THERM_STATUS_POWER_LIMIT       (1 << 10)
> +#define PACKAGE_THERM_STATUS_HFI_UPDATED       (1 << 26)
>
>  #define MSR_IA32_PACKAGE_THERM_INTERRUPT       0x000001b2
>
>  #define PACKAGE_THERM_INT_HIGH_ENABLE          (1 << 0)
>  #define PACKAGE_THERM_INT_LOW_ENABLE           (1 << 1)
>  #define PACKAGE_THERM_INT_PLN_ENABLE           (1 << 24)
> +#define PACKAGE_THERM_INT_HFI_ENABLE           (1 << 25)
>
>  /* Thermal Thresholds Support */
>  #define THERM_INT_THRESHOLD0_ENABLE    (1 << 15)
> @@ -941,4 +943,8 @@
>  #define MSR_VM_IGNNE                    0xc0010115
>  #define MSR_VM_HSAVE_PA                 0xc0010117
>
> +/* Hardware Feedback Interface */
> +#define MSR_IA32_HW_FEEDBACK_PTR        0x17d0
> +#define MSR_IA32_HW_FEEDBACK_CONFIG     0x17d1
> +
>  #endif /* _ASM_X86_MSR_INDEX_H */
> --
> 2.17.1
>
Borislav Petkov Dec. 30, 2021, 6:13 p.m. UTC | #2
On Thu, Dec 30, 2021 at 07:03:57PM +0100, Rafael J. Wysocki wrote:

> Subject: Re: [PATCH v2 2/7] x86: Add definitions for the Intel Hardware Feedback Interface

Make that subject prefix "x86/cpu:" when committing pls.

With that:

Acked-by: Borislav Petkov <bp@suse.de>

Thx.
Ricardo Neri Jan. 2, 2022, 9:35 p.m. UTC | #3
On Thu, Dec 30, 2021 at 07:13:09PM +0100, Borislav Petkov wrote:
> On Thu, Dec 30, 2021 at 07:03:57PM +0100, Rafael J. Wysocki wrote:
> 
> > Subject: Re: [PATCH v2 2/7] x86: Add definitions for the Intel Hardware Feedback Interface
> 
> Make that subject prefix "x86/cpu:" when committing pls.
> 
> With that:
> 
> Acked-by: Borislav Petkov <bp@suse.de>
> 
> Thx.

Thank you Boris. I will make the requested change.

BR,
Ricardo
diff mbox series

Patch

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index d5b5f2ab87a0..1a31b3ef15f0 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -327,6 +327,7 @@ 
 #define X86_FEATURE_HWP_ACT_WINDOW	(14*32+ 9) /* HWP Activity Window */
 #define X86_FEATURE_HWP_EPP		(14*32+10) /* HWP Energy Perf. Preference */
 #define X86_FEATURE_HWP_PKG_REQ		(14*32+11) /* HWP Package Level Request */
+#define X86_FEATURE_HFI			(14*32+19) /* Hardware Feedback Interface */
 
 /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
 #define X86_FEATURE_NPT			(15*32+ 0) /* Nested Page Table support */
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 01e2650b9585..ad958a49b2bb 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -687,12 +687,14 @@ 
 
 #define PACKAGE_THERM_STATUS_PROCHOT		(1 << 0)
 #define PACKAGE_THERM_STATUS_POWER_LIMIT	(1 << 10)
+#define PACKAGE_THERM_STATUS_HFI_UPDATED	(1 << 26)
 
 #define MSR_IA32_PACKAGE_THERM_INTERRUPT	0x000001b2
 
 #define PACKAGE_THERM_INT_HIGH_ENABLE		(1 << 0)
 #define PACKAGE_THERM_INT_LOW_ENABLE		(1 << 1)
 #define PACKAGE_THERM_INT_PLN_ENABLE		(1 << 24)
+#define PACKAGE_THERM_INT_HFI_ENABLE		(1 << 25)
 
 /* Thermal Thresholds Support */
 #define THERM_INT_THRESHOLD0_ENABLE    (1 << 15)
@@ -941,4 +943,8 @@ 
 #define MSR_VM_IGNNE                    0xc0010115
 #define MSR_VM_HSAVE_PA                 0xc0010117
 
+/* Hardware Feedback Interface */
+#define MSR_IA32_HW_FEEDBACK_PTR        0x17d0
+#define MSR_IA32_HW_FEEDBACK_CONFIG     0x17d1
+
 #endif /* _ASM_X86_MSR_INDEX_H */