diff mbox series

[v2,10/17] dt-bindings: spi: add bindings for microchip mpfs spi

Message ID 20211217093325.30612-11-conor.dooley@microchip.com
State New
Headers show
Series Update the Icicle Kit device tree | expand

Commit Message

Conor Dooley Dec. 17, 2021, 9:33 a.m. UTC
From: Conor Dooley <conor.dooley@microchip.com>

Add device tree bindings for the {q,}spi controller on
the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../bindings/spi/microchip,mpfs-spi.yaml      | 61 +++++++++++++++++++
 1 file changed, 61 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml

Comments

Conor Dooley Dec. 20, 2021, 8:05 a.m. UTC | #1
On 17/12/2021 11:43, Mark Brown wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you 
know the content is safe
>
> On Fri, Dec 17, 2021 at 11:40:29AM +0000, Conor.Dooley@microchip.com 
wrote:
>> On 17/12/2021 11:17, Mark Brown wrote:
>>> Why do you need this property in the DT - isn't the number of chip
>>> selects in the IP a fixes property?
>>
>> Nope! It's an IP that's intended for use in FPGAs so the number of
>> selects may (and does) vary based on implementation.
>
> That doesn't explain why the number is needed in the binding - why do
> you need this property in the DT?

Took another look at the IP core configuration & I think you're right 
and that property can be dropped. The register responsible for CS 
control will not be optimised away even if the CS is not used & the 
worst outcome is that nothing will happen.
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
new file mode 100644
index 000000000000..fe257b3384a9
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
@@ -0,0 +1,61 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS {Q,}SPI Controller Device Tree Bindings
+
+maintainers:
+  - Conor Dooley <conor.dooley@microchip.com>
+
+allOf:
+  - $ref: spi-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - microchip,mpfs-spi
+      - microchip,mpfs-qspi
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clock-names:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  num-cs:
+    description: |
+      Number of chip selects used.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 1
+    maximum: 8
+    default: 8
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include "dt-bindings/clock/microchip,mpfs-clock.h"
+    spi0: spi@20108000 {
+        compatible = "microchip,mpfs-spi";
+        reg = <0x20108000 0x1000>;
+        clocks = <&clkcfg CLK_SPI0>;
+        interrupt-parent = <&plic>;
+        interrupts = <54>;
+        spi-max-frequency = <25000000>;
+        num-cs = <8>;
+    };
+...