diff mbox series

[v5,15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump

Message ID 20211019152438.269077-16-richard.henderson@linaro.org
State Superseded
Headers show
Series target/riscv: Rationalize XLEN and operand length | expand

Commit Message

Richard Henderson Oct. 19, 2021, 3:24 p.m. UTC 
Use the official debug read interface to the csrs,
rather than referencing the env slots directly.
Put the list of csrs to dump into a table.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/riscv/cpu.c | 90 +++++++++++++++++++++++-----------------------
 1 file changed, 46 insertions(+), 44 deletions(-)

-- 
2.25.1

Comments

Alistair Francis Oct. 19, 2021, 10:12 p.m. UTC | #1 
On Wed, Oct 20, 2021 at 2:50 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Use the official debug read interface to the csrs,

> rather than referencing the env slots directly.

> Put the list of csrs to dump into a table.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Alistair Francis <alistair.francis@wdc.com>


Alistair

> ---

>  target/riscv/cpu.c | 90 +++++++++++++++++++++++-----------------------

>  1 file changed, 46 insertions(+), 44 deletions(-)

>

> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c

> index f352c2b74c..3454b19c17 100644

> --- a/target/riscv/cpu.c

> +++ b/target/riscv/cpu.c

> @@ -241,52 +241,54 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)

>      }

>  #endif

>      qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", "pc", env->pc);

> +

>  #ifndef CONFIG_USER_ONLY

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);

> -    if (riscv_cpu_mxl(env) == MXL_RV32) {

> -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",

> -                     (target_ulong)(env->mstatus >> 32));

> +    {

> +        static const int dump_csrs[] = {

> +            CSR_MHARTID,

> +            CSR_MSTATUS,

> +            CSR_MSTATUSH,

> +            CSR_HSTATUS,

> +            CSR_VSSTATUS,

> +            CSR_MIP,

> +            CSR_MIE,

> +            CSR_MIDELEG,

> +            CSR_HIDELEG,

> +            CSR_MEDELEG,

> +            CSR_HEDELEG,

> +            CSR_MTVEC,

> +            CSR_STVEC,

> +            CSR_VSTVEC,

> +            CSR_MEPC,

> +            CSR_SEPC,

> +            CSR_VSEPC,

> +            CSR_MCAUSE,

> +            CSR_SCAUSE,

> +            CSR_VSCAUSE,

> +            CSR_MTVAL,

> +            CSR_STVAL,

> +            CSR_HTVAL,

> +            CSR_MTVAL2,

> +            CSR_MSCRATCH,

> +            CSR_SSCRATCH,

> +            CSR_SATP,

> +        };

> +

> +        for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {

> +            int csrno = dump_csrs[i];

> +            target_ulong val = 0;

> +            RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);

> +

> +            /*

> +             * Rely on the smode, hmode, etc, predicates within csr.c

> +             * to do the filtering of the registers that are present.

> +             */

> +            if (res == RISCV_EXCP_NONE) {

> +                qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",

> +                             csr_ops[csrno].name, val);

> +            }

> +        }

>      }

> -    if (riscv_has_ext(env, RVH)) {

> -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);

> -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",

> -                     (target_ulong)env->vsstatus);

> -    }

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);

> -    if (riscv_has_ext(env, RVH)) {

> -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);

> -    }

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);

> -    if (riscv_has_ext(env, RVH)) {

> -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);

> -    }

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);

> -    if (riscv_has_ext(env, RVH)) {

> -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);

> -    }

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);

> -    if (riscv_has_ext(env, RVH)) {

> -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);

> -    }

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);

> -    if (riscv_has_ext(env, RVH)) {

> -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);

> -    }

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval   ", env->mtval);

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval   ", env->stval);

> -    if (riscv_has_ext(env, RVH)) {

> -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);

> -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);

> -    }

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);

> -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp    ", env->satp);

>  #endif

>

>      for (i = 0; i < 32; i++) {

> --

> 2.25.1

>

>
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f352c2b74c..3454b19c17 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -241,52 +241,54 @@  static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
     }
 #endif
     qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", "pc", env->pc);
+
 #ifndef CONFIG_USER_ONLY
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
-    if (riscv_cpu_mxl(env) == MXL_RV32) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
-                     (target_ulong)(env->mstatus >> 32));
+    {
+        static const int dump_csrs[] = {
+            CSR_MHARTID,
+            CSR_MSTATUS,
+            CSR_MSTATUSH,
+            CSR_HSTATUS,
+            CSR_VSSTATUS,
+            CSR_MIP,
+            CSR_MIE,
+            CSR_MIDELEG,
+            CSR_HIDELEG,
+            CSR_MEDELEG,
+            CSR_HEDELEG,
+            CSR_MTVEC,
+            CSR_STVEC,
+            CSR_VSTVEC,
+            CSR_MEPC,
+            CSR_SEPC,
+            CSR_VSEPC,
+            CSR_MCAUSE,
+            CSR_SCAUSE,
+            CSR_VSCAUSE,
+            CSR_MTVAL,
+            CSR_STVAL,
+            CSR_HTVAL,
+            CSR_MTVAL2,
+            CSR_MSCRATCH,
+            CSR_SSCRATCH,
+            CSR_SATP,
+        };
+
+        for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
+            int csrno = dump_csrs[i];
+            target_ulong val = 0;
+            RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
+
+            /*
+             * Rely on the smode, hmode, etc, predicates within csr.c
+             * to do the filtering of the registers that are present.
+             */
+            if (res == RISCV_EXCP_NONE) {
+                qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
+                             csr_ops[csrno].name, val);
+            }
+        }
     }
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
-                     (target_ulong)env->vsstatus);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval   ", env->mtval);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval   ", env->stval);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp    ", env->satp);
 #endif
 
     for (i = 0; i < 32; i++) {