diff mbox series

[11/13] target/riscv: Adjust trans_rev8_32 for riscv64

Message ID 20211007174722.929993-12-richard.henderson@linaro.org
State Superseded
Headers show
Series target/riscv: Rationalize XLEN and operand length | expand

Commit Message

Richard Henderson Oct. 7, 2021, 5:47 p.m. UTC
When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

-- 
2.25.1

Comments

LIU Zhiwei Oct. 13, 2021, 11:45 a.m. UTC | #1
On 2021/10/8 上午1:47, Richard Henderson wrote:

> When target_long is 64-bit, we still want a 32-bit bswap for rev8.

> Since this opcode is specific to RV32, we need not conditionalize.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>


Zhiwei
> ---

>   target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-

>   1 file changed, 6 insertions(+), 1 deletion(-)

>

> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc

> index 66dd51de49..c62eea433a 100644

> --- a/target/riscv/insn_trans/trans_rvb.c.inc

> +++ b/target/riscv/insn_trans/trans_rvb.c.inc

> @@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)

>       return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);

>   }

>   

> +static void gen_rev8_32(TCGv ret, TCGv src1)

> +{

> +    tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);

> +}

> +

>   static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)

>   {

>       REQUIRE_32BIT(ctx);

>       REQUIRE_ZBB(ctx);

> -    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);

> +    return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);

>   }

>   

>   static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 66dd51de49..c62eea433a 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -232,11 +232,16 @@  static bool trans_rol(DisasContext *ctx, arg_rol *a)
     return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
 }
 
+static void gen_rev8_32(TCGv ret, TCGv src1)
+{
+    tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
+}
+
 static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
 {
     REQUIRE_32BIT(ctx);
     REQUIRE_ZBB(ctx);
-    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
+    return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
 }
 
 static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)