[1/8] tcg: Add TCG_TARGET_SIGNED_ADDR32

Message ID	20211010174401.141339-2-richard.henderson@linaro.org
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Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH 1/8] tcg: Add TCG_TARGET_SIGNED_ADDR32 Date: Sun, 10 Oct 2021 10:43:54 -0700 Message-Id: <20211010174401.141339-2-richard.henderson@linaro.org> In-Reply-To: <20211010174401.141339-1-richard.henderson@linaro.org> References: <20211010174401.141339-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Cc: git@xen0n.name, Alistair.Francis@wdc.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	tcg: support 32-bit guest addresses as signed \| expand [0/8] tcg: support 32-bit guest addresses as signed [1/8] tcg: Add TCG_TARGET_SIGNED_ADDR32 [2/8] accel/tcg: Split out g2h_tlbe [3/8] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu [4/8] accel/tcg: Add guest_base_signed_addr32 for user-only [5/8] linux-user: Support TCG_TARGET_SIGNED_ADDR32 [6/8] tcg/aarch64: Support TCG_TARGET_SIGNED_ADDR32 [7/8] target/mips: Support TCG_TARGET_SIGNED_ADDR32 [8/8] target/riscv: Support TCG_TARGET_SIGNED_ADDR32

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20211010174401.141339-2-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
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Subject: [PATCH 1/8] tcg: Add TCG_TARGET_SIGNED_ADDR32
Date: Sun, 10 Oct 2021 10:43:54 -0700
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Series

tcg: support 32-bit guest addresses as signed | expand

Commit Message

Richard Henderson Oct. 10, 2021, 5:43 p.m. UTC

Define as 0 for all tcg hosts.  Put this in a separate header,
because we'll want this in places that do not ordinarily have
access to all of tcg/tcg.h.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 tcg/aarch64/tcg-target-sa32.h | 1 +
 tcg/arm/tcg-target-sa32.h     | 1 +
 tcg/i386/tcg-target-sa32.h    | 1 +
 tcg/mips/tcg-target-sa32.h    | 1 +
 tcg/ppc/tcg-target-sa32.h     | 1 +
 tcg/riscv/tcg-target-sa32.h   | 1 +
 tcg/s390x/tcg-target-sa32.h   | 1 +
 tcg/sparc/tcg-target-sa32.h   | 1 +
 tcg/tci/tcg-target-sa32.h     | 1 +
 9 files changed, 9 insertions(+)
 create mode 100644 tcg/aarch64/tcg-target-sa32.h
 create mode 100644 tcg/arm/tcg-target-sa32.h
 create mode 100644 tcg/i386/tcg-target-sa32.h
 create mode 100644 tcg/mips/tcg-target-sa32.h
 create mode 100644 tcg/ppc/tcg-target-sa32.h
 create mode 100644 tcg/riscv/tcg-target-sa32.h
 create mode 100644 tcg/s390x/tcg-target-sa32.h
 create mode 100644 tcg/sparc/tcg-target-sa32.h
 create mode 100644 tcg/tci/tcg-target-sa32.h

-- 
2.25.1

Comments

WANG Xuerui Oct. 11, 2021, 4:21 a.m. UTC | #1

On 2021/10/11 01:43, Richard Henderson wrote:
> Define as 0 for all tcg hosts.  Put this in a separate header,

> because we'll want this in places that do not ordinarily have

> access to all of tcg/tcg.h.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  tcg/aarch64/tcg-target-sa32.h | 1 +

>  tcg/arm/tcg-target-sa32.h     | 1 +

>  tcg/i386/tcg-target-sa32.h    | 1 +

>  tcg/mips/tcg-target-sa32.h    | 1 +

>  tcg/ppc/tcg-target-sa32.h     | 1 +

>  tcg/riscv/tcg-target-sa32.h   | 1 +

>  tcg/s390x/tcg-target-sa32.h   | 1 +

>  tcg/sparc/tcg-target-sa32.h   | 1 +

>  tcg/tci/tcg-target-sa32.h     | 1 +

>  9 files changed, 9 insertions(+)

>  create mode 100644 tcg/aarch64/tcg-target-sa32.h

>  create mode 100644 tcg/arm/tcg-target-sa32.h

>  create mode 100644 tcg/i386/tcg-target-sa32.h

>  create mode 100644 tcg/mips/tcg-target-sa32.h

>  create mode 100644 tcg/ppc/tcg-target-sa32.h

>  create mode 100644 tcg/riscv/tcg-target-sa32.h

>  create mode 100644 tcg/s390x/tcg-target-sa32.h

>  create mode 100644 tcg/sparc/tcg-target-sa32.h

>  create mode 100644 tcg/tci/tcg-target-sa32.h

Reviewed-by: WANG Xuerui <git@xen0n.name>

Alex Bennée Oct. 11, 2021, 9:55 a.m. UTC | #2

Richard Henderson <richard.henderson@linaro.org> writes:

> Define as 0 for all tcg hosts.  Put this in a separate header,

> because we'll want this in places that do not ordinarily have

> access to all of tcg/tcg.h.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Alex Bennée <alex.bennee@linaro.org>


-- 
Alex Bennée

Philippe Mathieu-Daudé Oct. 11, 2021, 10:07 p.m. UTC | #3

On 10/10/21 19:43, Richard Henderson wrote:
> Define as 0 for all tcg hosts.  Put this in a separate header,

> because we'll want this in places that do not ordinarily have

> access to all of tcg/tcg.h.

> 

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  tcg/aarch64/tcg-target-sa32.h | 1 +

>  tcg/arm/tcg-target-sa32.h     | 1 +

>  tcg/i386/tcg-target-sa32.h    | 1 +

>  tcg/mips/tcg-target-sa32.h    | 1 +

>  tcg/ppc/tcg-target-sa32.h     | 1 +

>  tcg/riscv/tcg-target-sa32.h   | 1 +

>  tcg/s390x/tcg-target-sa32.h   | 1 +

>  tcg/sparc/tcg-target-sa32.h   | 1 +

>  tcg/tci/tcg-target-sa32.h     | 1 +

>  9 files changed, 9 insertions(+)


Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Alistair Francis Oct. 11, 2021, 11:16 p.m. UTC | #4

On Mon, Oct 11, 2021 at 3:49 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Define as 0 for all tcg hosts.  Put this in a separate header,

> because we'll want this in places that do not ordinarily have

> access to all of tcg/tcg.h.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Alistair Francis <alistair.francis@wdc.com>


Alistair

> ---

>  tcg/aarch64/tcg-target-sa32.h | 1 +

>  tcg/arm/tcg-target-sa32.h     | 1 +

>  tcg/i386/tcg-target-sa32.h    | 1 +

>  tcg/mips/tcg-target-sa32.h    | 1 +

>  tcg/ppc/tcg-target-sa32.h     | 1 +

>  tcg/riscv/tcg-target-sa32.h   | 1 +

>  tcg/s390x/tcg-target-sa32.h   | 1 +

>  tcg/sparc/tcg-target-sa32.h   | 1 +

>  tcg/tci/tcg-target-sa32.h     | 1 +

>  9 files changed, 9 insertions(+)

>  create mode 100644 tcg/aarch64/tcg-target-sa32.h

>  create mode 100644 tcg/arm/tcg-target-sa32.h

>  create mode 100644 tcg/i386/tcg-target-sa32.h

>  create mode 100644 tcg/mips/tcg-target-sa32.h

>  create mode 100644 tcg/ppc/tcg-target-sa32.h

>  create mode 100644 tcg/riscv/tcg-target-sa32.h

>  create mode 100644 tcg/s390x/tcg-target-sa32.h

>  create mode 100644 tcg/sparc/tcg-target-sa32.h

>  create mode 100644 tcg/tci/tcg-target-sa32.h

>

> diff --git a/tcg/aarch64/tcg-target-sa32.h b/tcg/aarch64/tcg-target-sa32.h

> new file mode 100644

> index 0000000000..cb185b1526

> --- /dev/null

> +++ b/tcg/aarch64/tcg-target-sa32.h

> @@ -0,0 +1 @@

> +#define TCG_TARGET_SIGNED_ADDR32 0

> diff --git a/tcg/arm/tcg-target-sa32.h b/tcg/arm/tcg-target-sa32.h

> new file mode 100644

> index 0000000000..cb185b1526

> --- /dev/null

> +++ b/tcg/arm/tcg-target-sa32.h

> @@ -0,0 +1 @@

> +#define TCG_TARGET_SIGNED_ADDR32 0

> diff --git a/tcg/i386/tcg-target-sa32.h b/tcg/i386/tcg-target-sa32.h

> new file mode 100644

> index 0000000000..cb185b1526

> --- /dev/null

> +++ b/tcg/i386/tcg-target-sa32.h

> @@ -0,0 +1 @@

> +#define TCG_TARGET_SIGNED_ADDR32 0

> diff --git a/tcg/mips/tcg-target-sa32.h b/tcg/mips/tcg-target-sa32.h

> new file mode 100644

> index 0000000000..cb185b1526

> --- /dev/null

> +++ b/tcg/mips/tcg-target-sa32.h

> @@ -0,0 +1 @@

> +#define TCG_TARGET_SIGNED_ADDR32 0

> diff --git a/tcg/ppc/tcg-target-sa32.h b/tcg/ppc/tcg-target-sa32.h

> new file mode 100644

> index 0000000000..cb185b1526

> --- /dev/null

> +++ b/tcg/ppc/tcg-target-sa32.h

> @@ -0,0 +1 @@

> +#define TCG_TARGET_SIGNED_ADDR32 0

> diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h

> new file mode 100644

> index 0000000000..cb185b1526

> --- /dev/null

> +++ b/tcg/riscv/tcg-target-sa32.h

> @@ -0,0 +1 @@

> +#define TCG_TARGET_SIGNED_ADDR32 0

> diff --git a/tcg/s390x/tcg-target-sa32.h b/tcg/s390x/tcg-target-sa32.h

> new file mode 100644

> index 0000000000..cb185b1526

> --- /dev/null

> +++ b/tcg/s390x/tcg-target-sa32.h

> @@ -0,0 +1 @@

> +#define TCG_TARGET_SIGNED_ADDR32 0

> diff --git a/tcg/sparc/tcg-target-sa32.h b/tcg/sparc/tcg-target-sa32.h

> new file mode 100644

> index 0000000000..cb185b1526

> --- /dev/null

> +++ b/tcg/sparc/tcg-target-sa32.h

> @@ -0,0 +1 @@

> +#define TCG_TARGET_SIGNED_ADDR32 0

> diff --git a/tcg/tci/tcg-target-sa32.h b/tcg/tci/tcg-target-sa32.h

> new file mode 100644

> index 0000000000..cb185b1526

> --- /dev/null

> +++ b/tcg/tci/tcg-target-sa32.h

> @@ -0,0 +1 @@

> +#define TCG_TARGET_SIGNED_ADDR32 0

> --

> 2.25.1

>

>

diff --git a/tcg/aarch64/tcg-target-sa32.h b/tcg/aarch64/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/aarch64/tcg-target-sa32.h
@@ -0,0 +1 @@ 
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/arm/tcg-target-sa32.h b/tcg/arm/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/arm/tcg-target-sa32.h
@@ -0,0 +1 @@ 
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/i386/tcg-target-sa32.h b/tcg/i386/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/i386/tcg-target-sa32.h
@@ -0,0 +1 @@ 
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/mips/tcg-target-sa32.h b/tcg/mips/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/mips/tcg-target-sa32.h
@@ -0,0 +1 @@ 
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/ppc/tcg-target-sa32.h b/tcg/ppc/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/ppc/tcg-target-sa32.h
@@ -0,0 +1 @@ 
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/riscv/tcg-target-sa32.h
@@ -0,0 +1 @@ 
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/s390x/tcg-target-sa32.h b/tcg/s390x/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/s390x/tcg-target-sa32.h
@@ -0,0 +1 @@ 
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/sparc/tcg-target-sa32.h b/tcg/sparc/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/sparc/tcg-target-sa32.h
@@ -0,0 +1 @@ 
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/tci/tcg-target-sa32.h b/tcg/tci/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/tci/tcg-target-sa32.h
@@ -0,0 +1 @@ 
+#define TCG_TARGET_SIGNED_ADDR32 0

[1/8] tcg: Add TCG_TARGET_SIGNED_ADDR32

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