Message ID | 20210914021633.26377-1-chun-jie.chen@mediatek.com |
---|---|
Headers | show |
Series | Mediatek MT8195 clock support | expand |
On Tue, Sep 14, 2021 at 10:17 AM Chun-Jie Chen <chun-jie.chen@mediatek.com> wrote: > > Add MT8195 topckgen clock controller which provides muxes, dividers > to handle variety clock selection in other IP blocks. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
On Tue, Sep 14, 2021 at 10:17 AM Chun-Jie Chen <chun-jie.chen@mediatek.com> wrote: > > Add MT8195 ipesys clock controller which provides clock gate > control for Image Process Engine. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
On Tue, Sep 14, 2021 at 10:18 AM Chun-Jie Chen <chun-jie.chen@mediatek.com> wrote: > > Add MT8195 vdosys0 clock controller which provides clock gate > control in video system. This is integrated with mtk-mmsys > driver which will populate device by platform_device_register_data > to start vdosys clock driver. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Quoting Chun-Jie Chen (2021-09-13 19:16:10) > This patch adds the new binding documentation for system clock > and functional clock on Mediatek MT8195. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > --- Applied to clk-next
Quoting Chun-Jie Chen (2021-09-13 19:16:12) > On MT8195, tuner_en_reg is moved to register offest 0x0. > If we only judge by tuner_en_reg, it may lead to wrong address. > Add tuner_en_bit to the check condition. And it has been confirmed, > on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by > clock square control. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > --- Applied to clk-next
Quoting Chun-Jie Chen (2021-09-13 19:16:14) > Release clock data when clock driver probe fail to fix > possible resource leak. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > --- Applied to clk-next
Quoting Chun-Jie Chen (2021-09-13 19:16:16) > Add MT8195 topckgen clock controller which provides muxes, dividers > to handle variety clock selection in other IP blocks. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > --- Applied to clk-next
Quoting Chun-Jie Chen (2021-09-13 19:16:18) > Add MT8195 infrastructure clock controller which provides > clock gate control for basic IP like pwm, uart, spi and so on. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > --- Applied to clk-next
Quoting Chun-Jie Chen (2021-09-13 19:16:20) > Add MT8195 ccusys clock controller which provides clock gate > control in Camera Computing Unit. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > --- Applied to clk-next
Quoting Chun-Jie Chen (2021-09-13 19:16:22) > Add MT8195 ipesys clock controller which provides clock gate > control for Image Process Engine. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > --- Applied to clk-next
Quoting Chun-Jie Chen (2021-09-13 19:16:24) > Add MT8195 scp adsp clock controller which provides clock gate > control for Audio DSP. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > --- Applied to clk-next
Quoting Chun-Jie Chen (2021-09-13 19:16:26) > Add MT8195 vdosys0 clock controller which provides clock gate > control in video system. This is integrated with mtk-mmsys > driver which will populate device by platform_device_register_data > to start vdosys clock driver. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > --- Applied to clk-next
Quoting Chun-Jie Chen (2021-09-13 19:16:28) > Add MT8195 vencsys clock controllers which provide clock gate > control for video encoder. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > --- Applied to clk-next
Quoting Chun-Jie Chen (2021-09-13 19:16:30) > Add MT8195 vppsys1 clock controller which provides clock gate > controller for Video Processor Pipe. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > --- Applied to clk-next
Quoting Chun-Jie Chen (2021-09-13 19:16:32) > Add MT8195 imp i2c wrapper clock controllers which provide clock gate > control in I2C IP blocks. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > --- Applied to clk-next