| Message ID | 20210910192757.2309100-7-atish.patra@wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v3,01/10] RISC-V: Remove the current perf implementation | expand |
On Fri, 10 Sep 2021 12:27:53 -0700, Atish Patra wrote: > This patch adds the DT bindings for RISC-V PMU driver. It also defines > the interrupt related properties to allow counter overflow interrupt. > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > --- > .../devicetree/bindings/perf/riscv,pmu.yaml | 51 +++++++++++++++++++ > 1 file changed, 51 insertions(+) > create mode 100644 Documentation/devicetree/bindings/perf/riscv,pmu.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/perf/riscv,pmu.yaml: 'optional' is not one of ['$id', '$schema', 'title', 'description', 'examples', 'required', 'allOf', 'anyOf', 'oneOf', 'definitions', '$defs', 'additionalProperties', 'dependencies', 'patternProperties', 'properties', 'if', 'then', 'else', 'unevaluatedProperties', 'deprecated', 'maintainers', 'select'] from schema $id: http://devicetree.org/meta-schemas/base.yaml# ./Documentation/devicetree/bindings/perf/riscv,pmu.yaml: $id: relative path/filename doesn't match actual path or filename expected: http://devicetree.org/schemas/perf/riscv,pmu.yaml# /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/perf/riscv,pmu.yaml: ignoring, error in schema: warning: no schema found in file: ./Documentation/devicetree/bindings/perf/riscv,pmu.yaml Documentation/devicetree/bindings/perf/riscv,pmu.example.dt.yaml:0:0: /example-0/pmu: failed to match any schema with compatible: ['riscv,pmu'] doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1526606 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Fri, Sep 10, 2021 at 12:27:53PM -0700, Atish Patra wrote: > This patch adds the DT bindings for RISC-V PMU driver. It also defines > the interrupt related properties to allow counter overflow interrupt. > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > --- > .../devicetree/bindings/perf/riscv,pmu.yaml | 51 +++++++++++++++++++ > 1 file changed, 51 insertions(+) > create mode 100644 Documentation/devicetree/bindings/perf/riscv,pmu.yaml > > diff --git a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml > new file mode 100644 > index 000000000000..497caad63f16 > --- /dev/null > +++ b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml > @@ -0,0 +1,51 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pmu/riscv,pmu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: RISC-V PMU > + > +maintainers: > + - Atish Patra <atish.patra@wdc.com> > + > +description: > + The "Sscofpmf" extension allows the RISC-V PMU counters to overflow and > + generate a local interrupt so that event sampling can be done from user-space. > + The above said ISA extension is an optional extension to maintain backward > + compatibility and will be included in privilege specification v1.12 . That's > + why the interrupt property is marked as optional. The platforms with sscofpmf > + extension should add this property to enable event sampling. > + The device tree node with the compatible string is mandatory for any platform > + that wants to use pmu counter start/stop methods using SBI PMU extension. > + > +properties: > + compatible: > + enum: > + - riscv,pmu > + > + description: > + Should be "riscv,pmu". The schema already says this. Just 'pmu' isn't very specific. No version to attach here? > + > + interrupts-extended: > + minItems: 1 > + maxItems: 4095 > + > +additionalProperties: false > + > +required: > + - None > +optional: > + - compatible Besides 'optional' not being the in vocabulary, 'compatible' is never optional. > + - interrupts-extended > + > +examples: > + - | > + pmu { > + compatible = "riscv,pmu"; > + interrupts-extended = <&cpu0intc 13>, > + <&cpu1intc 13>, > + <&cpu2intc 13>, > + <&cpu3intc 13>; > + }; > +... > -- > 2.31.1 > >
diff --git a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file mode 100644 index 000000000000..497caad63f16 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pmu/riscv,pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V PMU + +maintainers: + - Atish Patra <atish.patra@wdc.com> + +description: + The "Sscofpmf" extension allows the RISC-V PMU counters to overflow and + generate a local interrupt so that event sampling can be done from user-space. + The above said ISA extension is an optional extension to maintain backward + compatibility and will be included in privilege specification v1.12 . That's + why the interrupt property is marked as optional. The platforms with sscofpmf + extension should add this property to enable event sampling. + The device tree node with the compatible string is mandatory for any platform + that wants to use pmu counter start/stop methods using SBI PMU extension. + +properties: + compatible: + enum: + - riscv,pmu + + description: + Should be "riscv,pmu". + + interrupts-extended: + minItems: 1 + maxItems: 4095 + +additionalProperties: false + +required: + - None +optional: + - compatible + - interrupts-extended + +examples: + - | + pmu { + compatible = "riscv,pmu"; + interrupts-extended = <&cpu0intc 13>, + <&cpu1intc 13>, + <&cpu2intc 13>, + <&cpu3intc 13>; + }; +...
This patch adds the DT bindings for RISC-V PMU driver. It also defines the interrupt related properties to allow counter overflow interrupt. Signed-off-by: Atish Patra <atish.patra@wdc.com> --- .../devicetree/bindings/perf/riscv,pmu.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/perf/riscv,pmu.yaml