| Message ID | 20210903180924.1006044-7-angelogioacchino.delregno@somainline.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | None | expand |
On Fri 03 Sep 11:09 PDT 2021, AngeloGioacchino Del Regno wrote: > All smartphones of this platform are equipped with a WCD9335 audio > codec, getting its MCLK from PM8998 gpio13: add this clock to DT. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi > index 5fbe5abf4133..7aeebd3b2e9e 100644 > --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi > @@ -20,6 +20,19 @@ / { > qcom,msm-id = <0x124 0x20000>, <0x124 0x20001>; /* 8998v2, v2.1 */ > qcom,board-id = <8 0>; > > + clocks { > + compatible = "simple-bus"; > + > + div1_mclk: divclk1 { > + compatible = "gpio-gate-clock"; > + pinctrl-0 = <&audio_mclk_pin>; > + pinctrl-names = "default"; > + clocks = <&rpmcc RPM_SMD_DIV_CLK1>; What controls the clock rate of divclk1? Regards, Bjorn > + #clock-cells = <0>; > + enable-gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; > + }; > + }; > + > board_vbat: vbat-regulator { > compatible = "regulator-fixed"; > regulator-name = "VBAT"; > @@ -313,6 +326,12 @@ cam_snapshot_pin_a: cam-snapshot-btn-active { > input-enable; > qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; > }; > + > + audio_mclk_pin: audio-mclk-pin-active { > + pins = "gpio13"; > + function = "func2"; > + power-source = <0>; > + }; > }; > > &pmi8998_gpio { > -- > 2.32.0 >
Il 07/09/21 15:47, Bjorn Andersson ha scritto: > On Fri 03 Sep 11:09 PDT 2021, AngeloGioacchino Del Regno wrote: > >> All smartphones of this platform are equipped with a WCD9335 audio >> codec, getting its MCLK from PM8998 gpio13: add this clock to DT. >> >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> >> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> >> --- >> .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 19 +++++++++++++++++++ >> 1 file changed, 19 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi >> index 5fbe5abf4133..7aeebd3b2e9e 100644 >> --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi >> +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi >> @@ -20,6 +20,19 @@ / { >> qcom,msm-id = <0x124 0x20000>, <0x124 0x20001>; /* 8998v2, v2.1 */ >> qcom,board-id = <8 0>; >> >> + clocks { >> + compatible = "simple-bus"; >> + >> + div1_mclk: divclk1 { >> + compatible = "gpio-gate-clock"; >> + pinctrl-0 = <&audio_mclk_pin>; >> + pinctrl-names = "default"; >> + clocks = <&rpmcc RPM_SMD_DIV_CLK1>; > > What controls the clock rate of divclk1? > That's going to be assigned to WCD9335 (oh btw, I have working audio locally! it's not great, but I can hear sounds from the internal speakers), but I haven't added the entire audio configuration in these submitted commits because: 1. It needs two GDSCs in GCC: adding them without enabling the lpass iommu will produce a crash, as the iommu would go off when the kernel starts turning off unused stuff... and we have secure contexts there, which means that the hypervisor will say hello; 2. The lpass iommu needs a commit in the qcom smmu implementation detail driver, as we need to select a different context (not the last ctx, but the one before) for bypass streams emulation, as the last one seems to be untouchable... small preview of the required commit: qsmmu->bypass_cbndx = [value from dt], or [default == smmu->num_context_banks-1] 3. We need the lpass iommu to get "the audio stuff" (surely, no need to list it). So that's the entire picture... I am planning to get this base merged in before going for a cleanup and submission of the rest of what I have here. Long story short: WCD9335 will be responsible for controlling this clock. Cheers, - Angelo > Regards, > Bjorn > >> + #clock-cells = <0>; >> + enable-gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; >> + }; >> + }; >> + >> board_vbat: vbat-regulator { >> compatible = "regulator-fixed"; >> regulator-name = "VBAT"; >> @@ -313,6 +326,12 @@ cam_snapshot_pin_a: cam-snapshot-btn-active { >> input-enable; >> qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; >> }; >> + >> + audio_mclk_pin: audio-mclk-pin-active { >> + pins = "gpio13"; >> + function = "func2"; >> + power-source = <0>; >> + }; >> }; >> >> &pmi8998_gpio { >> -- >> 2.32.0 >>
diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 5fbe5abf4133..7aeebd3b2e9e 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -20,6 +20,19 @@ / { qcom,msm-id = <0x124 0x20000>, <0x124 0x20001>; /* 8998v2, v2.1 */ qcom,board-id = <8 0>; + clocks { + compatible = "simple-bus"; + + div1_mclk: divclk1 { + compatible = "gpio-gate-clock"; + pinctrl-0 = <&audio_mclk_pin>; + pinctrl-names = "default"; + clocks = <&rpmcc RPM_SMD_DIV_CLK1>; + #clock-cells = <0>; + enable-gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; + }; + }; + board_vbat: vbat-regulator { compatible = "regulator-fixed"; regulator-name = "VBAT"; @@ -313,6 +326,12 @@ cam_snapshot_pin_a: cam-snapshot-btn-active { input-enable; qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; }; + + audio_mclk_pin: audio-mclk-pin-active { + pins = "gpio13"; + function = "func2"; + power-source = <0>; + }; }; &pmi8998_gpio {