| Message ID | 1630643340-10373-1-git-send-email-rajpat@codeaurora.org |
|---|---|
| Headers | show |
| Series | Add QSPI and QUPv3 DT nodes for SC7280 SoC | expand |
On Fri, Sep 03, 2021 at 09:58:59AM +0530, Rajesh Patil wrote: > From: Roja Rani Yarubandi <rojay@codeaurora.org> > > Add QUPv3 wrapper_1 DT nodes for SC7280 SoC. > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 709 +++++++++++++++++++++++++++++++++++ > 1 file changed, 709 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 32d1354..8fe54bf 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > + qup_spi8_data_clk: qup-spi8-data-clk { > + pins = "gpio32", "gpio33", "gpio34"; > + function = "qup10"; > + }; > + > + qup_spi8_cs: qup-spi8-cs { > + pins = "gpio35"; > + function = "qup10"; > + }; As for wrapper_0, I think we still want the nodes to configure the CS as GPIO. If there are no other reasons to re-spin these could be added with a follow-up patch, so: Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
On 2021-09-03 22:52, Matthias Kaehlcke wrote: > On Fri, Sep 03, 2021 at 09:58:59AM +0530, Rajesh Patil wrote: >> From: Roja Rani Yarubandi <rojay@codeaurora.org> >> >> Add QUPv3 wrapper_1 DT nodes for SC7280 SoC. >> >> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> >> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 709 >> +++++++++++++++++++++++++++++++++++ >> 1 file changed, 709 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 32d1354..8fe54bf 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > >> + qup_spi8_data_clk: qup-spi8-data-clk { >> + pins = "gpio32", "gpio33", "gpio34"; >> + function = "qup10"; >> + }; >> + >> + qup_spi8_cs: qup-spi8-cs { >> + pins = "gpio35"; >> + function = "qup10"; >> + }; > > As for wrapper_0, I think we still want the nodes to configure the CS > as GPIO. > > If there are no other reasons to re-spin these could be added with a > follow-up > patch, so: > shall we add all removed qup_spiN_cs_gpio nodes? > Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
On Thu, Sep 09, 2021 at 10:14:18AM +0530, rajpat@codeaurora.org wrote: > On 2021-09-03 22:52, Matthias Kaehlcke wrote: > > On Fri, Sep 03, 2021 at 09:58:59AM +0530, Rajesh Patil wrote: > > > From: Roja Rani Yarubandi <rojay@codeaurora.org> > > > > > > Add QUPv3 wrapper_1 DT nodes for SC7280 SoC. > > > > > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> > > > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> > > > --- > > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 709 > > > +++++++++++++++++++++++++++++++++++ > > > 1 file changed, 709 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi > > > b/arch/arm64/boot/dts/qcom/sc7280.dtsi > > > index 32d1354..8fe54bf 100644 > > > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > > > > > + qup_spi8_data_clk: qup-spi8-data-clk { > > > + pins = "gpio32", "gpio33", "gpio34"; > > > + function = "qup10"; > > > + }; > > > + > > > + qup_spi8_cs: qup-spi8-cs { > > > + pins = "gpio35"; > > > + function = "qup10"; > > > + }; > > > > As for wrapper_0, I think we still want the nodes to configure the CS as > > GPIO. > > > > If there are no other reasons to re-spin these could be added with a > > follow-up > > patch, so: > > > shall we add all removed qup_spiN_cs_gpio nodes? Yes
Changes in V7: - As per Stephen's comments 1. Moved qup_opp_table under /soc@0/geniqup@9c0000 2. Removed qupv3_id_1 in sc7280-idp board file 3. Sorted alias names for i2c and spi as per alphabet order - As per Matthias comment Configuring cs pin with gpio (qup_spiN_cs_gpio) definitions are removed Changes in V6: - As per Matthias' comments, 1. Squashed "Update QUPv3 UART5 DT node" and "Configure debug uart for sc7280-idp" 2. Moved qup_opp_table from /soc to / 3. Changed convention "clocks" followed by "clock-names" - As per Doug comments, added aliases for i2c and spi Changes in V5: - As per Matthias' comments, I've split the patches as below: 1. Add QSPI node 2. Configure SPI-NOR FLASH for sc7280-idp 3. Add QUPv3 wrapper_0 nodes 4. Update QUPv3 UART5 DT node 5. Configure debug uart for sc7280-idp 6. Configure uart7 to support bluetooth on sc7280-idp 7. Add QUPv3 wrapper_1 nodes Changes in V4: - As per Stephen's comment updated spi-max-frequency to 37.5MHz, moved qspi_opp_table from /soc to / (root). - As per Bjorn's comment, added QUP Wrapper_0 nodes as separate patch and debug-uart node as separate patch. - Dropped interconnect votes for wrapper_0 and wrapper_1 node - Corrected QUP Wrapper_1 SE node's pin control functions like below QUP Wrapper_0: SE0-SE7 uses qup00 - qup07 pin-cntrl functions. QUP Wrapper_1: SE0-SE7 uses qup10 - qup17 pin-cntrl functions. Changes in V3: - Broken the huge V2 patch into 3 smaller patches. 1. QSPI DT nodes 2. QUP wrapper_0 DT nodes 3. QUP wrapper_1 DT nodes Changes in V2: - As per Doug's comments removed pinmux/pinconf subnodes. - As per Doug's comments split of SPI, UART nodes has been done. - Moved QSPI node before aps_smmu as per the order. Rajesh Patil (3): arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp arm64: dts: sc7280: Configure uart7 to support bluetooth on sc7280-idp arm64: dts: sc7280: Add aliases for I2C and SPI Roja Rani Yarubandi (4): arm64: dts: sc7280: Add QSPI node arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes arm64: dts: sc7280: Update QUPv3 UART5 DT node arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 125 ++- arch/arm64/boot/dts/qcom/sc7280.dtsi | 1520 +++++++++++++++++++++++++++++- 2 files changed, 1628 insertions(+), 17 deletions(-)