| Message ID | 20210902225750.29313-2-samuel@sholland.org |
|---|---|
| State | Accepted |
| Commit | 55f36df9ec4f6c53b6a06acfc4195e99bd9355fa |
| Headers | show |
| Series | Allwinner R329 and D1 watchdog support | expand |
On Thu, Sep 02, 2021 at 05:57:48PM -0500, Samuel Holland wrote: > On existing SoCs, the watchdog has a single clock input: HOSC (OSC24M) > divided by 750. However, starting with R329, LOSC (OSC32k) is added as > an alternative clock source, with a bit to switch between them. > > Since 24 MHz / 750 == 32 kHz, not 32.768 kHz, the hardware adjusts the > cycle counts to keep the timeouts independent of the clock source. This > keeps the programming interface backward-compatible. > > Furthermore, the R329 has two watchdogs: one for use by the ARM CPUs > at 0x20000a0, and a second one for use by the DSPs at 0x7020400. The > first of these adds two more new registers, to allow software to > immediately assert the SoC reset signal. Add an additional "-reset" > suffix to signify the presence of this feature. > > Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Maxime Ripard <maxime@cerno.tech> Thanks! Maxime
On Thu, 02 Sep 2021 17:57:48 -0500, Samuel Holland wrote: > On existing SoCs, the watchdog has a single clock input: HOSC (OSC24M) > divided by 750. However, starting with R329, LOSC (OSC32k) is added as > an alternative clock source, with a bit to switch between them. > > Since 24 MHz / 750 == 32 kHz, not 32.768 kHz, the hardware adjusts the > cycle counts to keep the timeouts independent of the clock source. This > keeps the programming interface backward-compatible. > > Furthermore, the R329 has two watchdogs: one for use by the ARM CPUs > at 0x20000a0, and a second one for use by the DSPs at 0x7020400. The > first of these adds two more new registers, to allow software to > immediately assert the SoC reset signal. Add an additional "-reset" > suffix to signify the presence of this feature. > > Signed-off-by: Samuel Holland <samuel@sholland.org> > --- > Changes v2 to v3: > - Add else case > - Add additional allwinner,sun50i-r329-wdt-reset compatible > Changes v1 to v2: > - Switch clock-names from enum to const > - Add descriptions to "clocks" items > > .../watchdog/allwinner,sun4i-a10-wdt.yaml | 42 ++++++++++++++++++- > 1 file changed, 41 insertions(+), 1 deletion(-) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 9aa3c313c49f..877f47759814 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -24,6 +24,8 @@ properties: - allwinner,sun50i-a100-wdt - allwinner,sun50i-h6-wdt - allwinner,sun50i-h616-wdt + - allwinner,sun50i-r329-wdt + - allwinner,sun50i-r329-wdt-reset - const: allwinner,sun6i-a31-wdt - items: - const: allwinner,suniv-f1c100s-wdt @@ -33,7 +35,18 @@ properties: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + items: + - description: High-frequency oscillator input, divided internally + - description: Low-frequency oscillator input, only found on some variants + + clock-names: + minItems: 1 + maxItems: 2 + items: + - const: hosc + - const: losc interrupts: maxItems: 1 @@ -44,6 +57,33 @@ required: - clocks - interrupts +if: + properties: + compatible: + contains: + enum: + - allwinner,sun50i-r329-wdt + - allwinner,sun50i-r329-wdt-reset + +then: + properties: + clocks: + minItems: 2 + + clock-names: + minItems: 2 + + required: + - clock-names + +else: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + unevaluatedProperties: false examples:
On existing SoCs, the watchdog has a single clock input: HOSC (OSC24M) divided by 750. However, starting with R329, LOSC (OSC32k) is added as an alternative clock source, with a bit to switch between them. Since 24 MHz / 750 == 32 kHz, not 32.768 kHz, the hardware adjusts the cycle counts to keep the timeouts independent of the clock source. This keeps the programming interface backward-compatible. Furthermore, the R329 has two watchdogs: one for use by the ARM CPUs at 0x20000a0, and a second one for use by the DSPs at 0x7020400. The first of these adds two more new registers, to allow software to immediately assert the SoC reset signal. Add an additional "-reset" suffix to signify the presence of this feature. Signed-off-by: Samuel Holland <samuel@sholland.org> --- Changes v2 to v3: - Add else case - Add additional allwinner,sun50i-r329-wdt-reset compatible Changes v1 to v2: - Switch clock-names from enum to const - Add descriptions to "clocks" items .../watchdog/allwinner,sun4i-a10-wdt.yaml | 42 ++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-)