Message ID | 20210830062451.639572-1-richard.henderson@linaro.org |
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[174.21.72.39]) by smtp.gmail.com with ESMTPSA id b12sm13942084pff.63.2021.08.29.23.24.52 for <qemu-devel@nongnu.org> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Aug 2021 23:24:52 -0700 (PDT) From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH 00/48] tcg: optimize redundant sign extensions Date: Sun, 29 Aug 2021 23:24:03 -0700 Message-Id: <20210830062451.639572-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org> |
Series |
tcg: optimize redundant sign extensions
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expand
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Hi Richard, On 8/30/21 8:24 AM, Richard Henderson wrote: > Currently, we have support for optimizing redundant zero extensions, > which I think was done with x86 and aarch64 in mind, which zero-extend > all 32-bit operations into the 64-bit register. > > But targets like Alpha, MIPS, and RISC-V do sign-extensions instead. > The last 5 patches address this. > > But before that, split the quite massive tcg_optimize function. Looks promising after quick review. Do you have any comparison perf numbers?
On 8/30/21 3:00 PM, Philippe Mathieu-Daudé wrote: > Hi Richard, > > On 8/30/21 8:24 AM, Richard Henderson wrote: >> Currently, we have support for optimizing redundant zero extensions, >> which I think was done with x86 and aarch64 in mind, which zero-extend >> all 32-bit operations into the 64-bit register. >> >> But targets like Alpha, MIPS, and RISC-V do sign-extensions instead. >> The last 5 patches address this. >> >> But before that, split the quite massive tcg_optimize function. > > Looks promising after quick review. Do you have any comparison perf numbers? No, not yet. I expect there to be *lots* of redundant extensions with the patches for RV32 on RV64. I think only MIPS n32 would compare, and I don't have a chroot for that, only n64. r~