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[v6,0/5] media: mediatek: support mdp3 on mt8183 platform

Message ID 20210819070954.16679-1-moudy.ho@mediatek.com
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Series media: mediatek: support mdp3 on mt8183 platform | expand

Message

Moudy Ho Aug. 19, 2021, 7:09 a.m. UTC 
Changes since v5:
- Rebase on v5.14-rc6.
- Move MMSYS/Mutex settings to corresponding driver.
- Revise the software license description and copyright.
- Remove unnecessary enum. or definitions.
- Optimize platform/chip definition conditions.
- Use general printing functions instead of MDP3 private ones.
- Fix compile warning.

Changes since v4:
- Rebase on v5.13-rc1.
- Remove the CMDQ flush flow to match the CMDQ API change.
- Integrate four of MDP's direct-link subcomponents into MDP controller node
  from syscon node to avoid illegal clock usage.
- Rewrite dt-binding in a JSON compatible subset of YAML
- Fix a bit of macro argument precedence.

Changes since v3:
- Rebase on v5.9-rc1.
- modify code for review comment from Rob Herring, cancel multiple nodes using
  same register base situation.
- control IOMMU port through pm runtime get/put to DMA components' device.
- SCP(VPU) driver revision.
- stop queuing jobs(remove flush_workqueue()) after mdp_m2m_release().
- add computation of plane address with data_offset.
- fix scale ratio check issue.
- add default v4l2_format setting.

Changes since v2:
- modify code for review comment from Tomasz Figa & Alexandre Courbot
- review comment from Rob Herring will offer code revision in v4, due to
  it's related to device node modification, will need to modify code
  architecture

Changes since v1:
- modify code for CMDQ v3 API support
- EC ipi cmd migration
- fix compliance test fail item (m2m cmd with -f) due to there is two problem in runing all format(-f) cmd:
1. out of memory before test complete
        Due to capture buffer mmap (refcount + 1) after reqbuf but seems
        no corresponding munmap called before device close.
        There are total 12XX items(formats) in format test and each format
        alloc 8 capture/output buffers.
2. unceasingly captureBufs() (randomly)
        Seems the break statement didn't catch the count == 0 situation:
        In v4l2-test-buffers.cpp, function: captureBufs()
                        ...
                        count--;
                        if (!node->is_m2m && !count)
                                break;
        Log is as attachment

I will paste the test result with problem part in another e-mail

Hi,

This is the first version of RFC patch for Media Data Path 3 (MDP3),
MDP3 is used for scaling and color format conversion.
support using GCE to write register in critical time limitation.
support V4L2 m2m device control.

Moudy Ho (5):
  soc: mediatek: mmsys: Add support for MDP
  soc: mediatek: mutex: add support for MDP
  dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
  dts: arm64: mt8183: Add Mediatek MDP3 nodes
  media: platform: mtk-mdp3: Add Mediatek MDP3 driver

 .../bindings/media/mediatek,mdp3-ccorr.yaml   |   58 +
 .../bindings/media/mediatek,mdp3-rdma.yaml    |  241 +++
 .../bindings/media/mediatek,mdp3-rsz.yaml     |   66 +
 .../bindings/media/mediatek,mdp3-wdma.yaml    |   71 +
 .../bindings/media/mediatek,mdp3-wrot.yaml    |   71 +
 arch/arm64/boot/dts/mediatek/mt8183.dtsi      |  110 ++
 drivers/media/platform/Kconfig                |   19 +
 drivers/media/platform/Makefile               |    2 +
 drivers/media/platform/mtk-mdp3/Makefile      |    7 +
 drivers/media/platform/mtk-mdp3/isp_reg.h     |   27 +
 .../media/platform/mtk-mdp3/mdp_reg_ccorr.h   |   19 +
 .../media/platform/mtk-mdp3/mdp_reg_rdma.h    |   65 +
 drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h |   39 +
 .../media/platform/mtk-mdp3/mdp_reg_wdma.h    |   47 +
 .../media/platform/mtk-mdp3/mdp_reg_wrot.h    |   55 +
 drivers/media/platform/mtk-mdp3/mtk-img-ipi.h |  281 ++++
 .../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c   |  508 ++++++
 .../media/platform/mtk-mdp3/mtk-mdp3-cmdq.h   |   47 +
 .../media/platform/mtk-mdp3/mtk-mdp3-comp.c   | 1357 +++++++++++++++++
 .../media/platform/mtk-mdp3/mtk-mdp3-comp.h   |  148 ++
 .../media/platform/mtk-mdp3/mtk-mdp3-core.c   |  300 ++++
 .../media/platform/mtk-mdp3/mtk-mdp3-core.h   |   75 +
 .../media/platform/mtk-mdp3/mtk-mdp3-m2m.c    |  802 ++++++++++
 .../media/platform/mtk-mdp3/mtk-mdp3-m2m.h    |   42 +
 .../media/platform/mtk-mdp3/mtk-mdp3-regs.c   |  747 +++++++++
 .../media/platform/mtk-mdp3/mtk-mdp3-regs.h   |  373 +++++
 .../media/platform/mtk-mdp3/mtk-mdp3-vpu.c    |  314 ++++
 .../media/platform/mtk-mdp3/mtk-mdp3-vpu.h    |   79 +
 drivers/soc/mediatek/mt8183-mmsys.h           |  235 +++
 drivers/soc/mediatek/mtk-mmsys.c              |  164 ++
 drivers/soc/mediatek/mtk-mmsys.h              |    9 +-
 drivers/soc/mediatek/mtk-mutex.c              |  106 +-
 include/linux/soc/mediatek/mtk-mmsys.h        |   81 +
 include/linux/soc/mediatek/mtk-mutex.h        |    8 +
 34 files changed, 6564 insertions(+), 9 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
 create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
 create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
 create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
 create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
 create mode 100644 drivers/media/platform/mtk-mdp3/Makefile
 create mode 100644 drivers/media/platform/mtk-mdp3/isp_reg.h
 create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_ccorr.h
 create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h
 create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h
 create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_wdma.h
 create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h
 create mode 100644 drivers/media/platform/mtk-mdp3/mtk-img-ipi.h
 create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
 create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h
 create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
 create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
 create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
 create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
 create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
 create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.h
 create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
 create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
 create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
 create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h

Comments

CK Hu (胡俊光) Aug. 24, 2021, 5:02 a.m. UTC | #1 
Hi, Moudy:

On Thu, 2021-08-19 at 15:09 +0800, Moudy Ho wrote:
> Add device nodes for Media Data Path 3 (MDP3) modules.

> 

> Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>

> Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com>

> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>

> ---

>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 110 +++++++++++++++++++++++

>  1 file changed, 110 insertions(+)

> 

> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi

> index f90df6439c08..7cb1fcfeefb6 100644

> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi

> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi

> @@ -1232,6 +1232,108 @@

>  			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;

>  		};

>  

> +		mdp3_rdma0: mdp3_rdma0@14001000 {

> +			compatible = "mediatek,mt8183-mdp3",

> +				     "mediatek,mt8183-mdp3-rdma";

> +			mediatek,scp = <&scp>;

> +			mediatek,mdp3-id = <0>;

> +			mdp3-comps = "mediatek,mt8183-mdp3-dl1", "mediatek,mt8183-mdp3-dl2",

> +				     "mediatek,mt8183-mdp3-path1", "mediatek,mt8183-mdp3-path2",

> +				     "mediatek,mt8183-mdp3-imgi", "mediatek,mt8183-mdp3-exto";

> +			mdp3-comp-ids = <0 1 0 1 0 1>;

> +			reg = <0 0x14001000 0 0x1000>,

> +			      <0 0x14000000 0 0x1000>,

> +			      <0 0x14005000 0 0x1000>,

> +			      <0 0x14006000 0 0x1000>,

> +			      <0 0x15020000 0 0x1000>;

> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>,

> +						  <&gce SUBSYS_1400XXXX 0 0x1000>,

> +						  <&gce SUBSYS_1400XXXX 0x5000 0x1000>,

> +						  <&gce SUBSYS_1400XXXX 0x6000 0x1000>,

> +						  <&gce SUBSYS_1502XXXX 0 0x1000>;

> +			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;

> +			clocks = <&mmsys CLK_MM_MDP_RDMA0>,

> +				 <&mmsys CLK_MM_MDP_RSZ1>,

> +				 <&mmsys CLK_MM_MDP_DL_TXCK>,

> +				 <&mmsys CLK_MM_MDP_DL_RX>,

> +				 <&mmsys CLK_MM_IPU_DL_TXCK>,

> +				 <&mmsys CLK_MM_IPU_DL_RX>;

> +			iommus = <&iommu M4U_PORT_MDP_RDMA0>;

> +			mediatek,mmsys = <&mmsys>;

> +			mediatek,mm-mutex = <&mutex>;

> +			mediatek,mailbox-gce = <&gce>;

> +			mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,

> +				 <&gce 21 CMDQ_THR_PRIO_LOWEST 0>,

> +				 <&gce 22 CMDQ_THR_PRIO_LOWEST 0>,

> +				 <&gce 23 CMDQ_THR_PRIO_LOWEST 0>;

> +			gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,

> +				     <&gce 0x14010000 SUBSYS_1401XXXX>,

> +				     <&gce 0x14020000 SUBSYS_1402XXXX>,

> +				     <&gce 0x15020000 SUBSYS_1502XXXX>;

> +			mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,

> +					      <CMDQ_EVENT_MDP_RDMA0_EOF>,

> +					      <CMDQ_EVENT_MDP_RSZ0_SOF>,


CMDQ_EVENT_MDP_RSZ0_SOF is sent from rsz0 to gce, so move this event to
rsz0.

Regards,
CK

> +					      <CMDQ_EVENT_MDP_RSZ1_SOF>,

> +					      <CMDQ_EVENT_MDP_TDSHP_SOF>,

> +					      <CMDQ_EVENT_MDP_WROT0_SOF>,

> +					      <CMDQ_EVENT_MDP_WROT0_EOF>,

> +					      <CMDQ_EVENT_MDP_WDMA0_SOF>,

> +					      <CMDQ_EVENT_MDP_WDMA0_EOF>,

> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,

> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,

> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,

> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,

> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,

> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,

> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,

> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,

> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,

> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,

> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,

> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,

> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,

> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,

> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,

> +					      <CMDQ_EVENT_WPE_A_DONE>,

> +					      <CMDQ_EVENT_SPE_B_DONE>;

> +		};

> +

> +		mdp3_rsz0: mdp3_rsz0@14003000 {

> +			compatible = "mediatek,mt8183-mdp3-rsz";

> +			mediatek,mdp3-id = <0>;

> +			reg = <0 0x14003000 0 0x1000>;

> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;

> +			clocks = <&mmsys CLK_MM_MDP_RSZ0>;

> +		};

> +

> +		mdp3_rsz1: mdp3_rsz1@14004000 {

> +			compatible = "mediatek,mt8183-mdp3-rsz";

> +			mediatek,mdp3-id = <1>;

> +			reg = <0 0x14004000 0 0x1000>;

> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;

> +			clocks = <&mmsys CLK_MM_MDP_RSZ1>;

> +		};

> +

> +		mdp3_wrot0: mdp3_wrot0@14005000 {

> +			compatible = "mediatek,mt8183-mdp3-wrot";

> +			mediatek,mdp3-id = <0>;

> +			reg = <0 0x14005000 0 0x1000>;

> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;

> +			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;

> +			clocks = <&mmsys CLK_MM_MDP_WROT0>;

> +			iommus = <&iommu M4U_PORT_MDP_WROT0>;

> +		};

> +

> +		mdp3_wdma: mdp3_wdma@14006000 {

> +			compatible = "mediatek,mt8183-mdp3-wdma";

> +			mediatek,mdp3-id = <0>;

> +			reg = <0 0x14006000 0 0x1000>;

> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;

> +			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;

> +			clocks = <&mmsys CLK_MM_MDP_WDMA0>;

> +			iommus = <&iommu M4U_PORT_MDP_WDMA0>;

> +		};

> +

>  		ovl0: ovl@14008000 {

>  			compatible = "mediatek,mt8183-disp-ovl";

>  			reg = <0 0x14008000 0 0x1000>;

> @@ -1378,6 +1480,14 @@

>  			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;

>  		};

>  

> +		mdp3_ccorr: mdp3_ccorr@1401c000 {

> +			compatible = "mediatek,mt8183-mdp3-ccorr";

> +			mediatek,mdp3-id = <0>;

> +			reg = <0 0x1401c000 0 0x1000>;

> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;

> +			clocks = <&mmsys CLK_MM_MDP_CCORR>;

> +		};

> +

>  		imgsys: syscon@15020000 {

>  			compatible = "mediatek,mt8183-imgsys", "syscon";

>  			reg = <0 0x15020000 0 0x1000>;