diff mbox series

[v5,17/24] target/riscv: Fix hgeie, hgeip

Message ID 20210823195529.560295-18-richard.henderson@linaro.org
State Accepted
Commit 377cbb4bdbe2ee4155d740bf1d7fc9a081a61219
Headers show
Series target/riscv: Use tcg_constant_* | expand

Commit Message

Richard Henderson Aug. 23, 2021, 7:55 p.m. UTC
We failed to write into *val for these read functions;
replace them with read_zero.  Only warn about unsupported
non-zero value when writing a non-zero value.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/riscv/csr.c | 26 ++++++++------------------
 1 file changed, 8 insertions(+), 18 deletions(-)

-- 
2.25.1

Comments

Bin Meng Aug. 24, 2021, 6:38 a.m. UTC | #1
On Tue, Aug 24, 2021 at 4:08 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> We failed to write into *val for these read functions;

> replace them with read_zero.  Only warn about unsupported

> non-zero value when writing a non-zero value.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/riscv/csr.c | 26 ++++++++------------------

>  1 file changed, 8 insertions(+), 18 deletions(-)

>


Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Alistair Francis Aug. 25, 2021, 6:09 a.m. UTC | #2
On Tue, Aug 24, 2021 at 6:08 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> We failed to write into *val for these read functions;

> replace them with read_zero.  Only warn about unsupported

> non-zero value when writing a non-zero value.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Alistair Francis <alistair.francis@wdc.com>


Alistair

> ---

>  target/riscv/csr.c | 26 ++++++++------------------

>  1 file changed, 8 insertions(+), 18 deletions(-)

>

> diff --git a/target/riscv/csr.c b/target/riscv/csr.c

> index d900f96dc1..905860dbb2 100644

> --- a/target/riscv/csr.c

> +++ b/target/riscv/csr.c

> @@ -1124,17 +1124,12 @@ static RISCVException write_hcounteren(CPURISCVState *env, int csrno,

>      return RISCV_EXCP_NONE;

>  }

>

> -static RISCVException read_hgeie(CPURISCVState *env, int csrno,

> -                                 target_ulong *val)

> -{

> -    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");

> -    return RISCV_EXCP_NONE;

> -}

> -

>  static RISCVException write_hgeie(CPURISCVState *env, int csrno,

>                                    target_ulong val)

>  {

> -    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");

> +    if (val) {

> +        qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");

> +    }

>      return RISCV_EXCP_NONE;

>  }

>

> @@ -1165,17 +1160,12 @@ static RISCVException write_htinst(CPURISCVState *env, int csrno,

>      return RISCV_EXCP_NONE;

>  }

>

> -static RISCVException read_hgeip(CPURISCVState *env, int csrno,

> -                                 target_ulong *val)

> -{

> -    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");

> -    return RISCV_EXCP_NONE;

> -}

> -

>  static RISCVException write_hgeip(CPURISCVState *env, int csrno,

>                                    target_ulong val)

>  {

> -    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");

> +    if (val) {

> +        qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");

> +    }

>      return RISCV_EXCP_NONE;

>  }

>

> @@ -1599,10 +1589,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {

>      [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },

>      [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },

>      [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },

> -    [CSR_HGEIE]       = { "hgeie",       hmode,   read_hgeie,       write_hgeie       },

> +    [CSR_HGEIE]       = { "hgeie",       hmode,   read_zero,        write_hgeie       },

>      [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },

>      [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },

> -    [CSR_HGEIP]       = { "hgeip",       hmode,   read_hgeip,       write_hgeip       },

> +    [CSR_HGEIP]       = { "hgeip",       hmode,   read_zero,        write_hgeip       },

>      [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },

>      [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },

>      [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },

> --

> 2.25.1

>

>
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d900f96dc1..905860dbb2 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1124,17 +1124,12 @@  static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
-static RISCVException read_hgeie(CPURISCVState *env, int csrno,
-                                 target_ulong *val)
-{
-    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
-    return RISCV_EXCP_NONE;
-}
-
 static RISCVException write_hgeie(CPURISCVState *env, int csrno,
                                   target_ulong val)
 {
-    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    if (val) {
+        qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    }
     return RISCV_EXCP_NONE;
 }
 
@@ -1165,17 +1160,12 @@  static RISCVException write_htinst(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
-static RISCVException read_hgeip(CPURISCVState *env, int csrno,
-                                 target_ulong *val)
-{
-    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
-    return RISCV_EXCP_NONE;
-}
-
 static RISCVException write_hgeip(CPURISCVState *env, int csrno,
                                   target_ulong val)
 {
-    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    if (val) {
+        qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    }
     return RISCV_EXCP_NONE;
 }
 
@@ -1599,10 +1589,10 @@  riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
     [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
-    [CSR_HGEIE]       = { "hgeie",       hmode,   read_hgeie,       write_hgeie       },
+    [CSR_HGEIE]       = { "hgeie",       hmode,   read_zero,        write_hgeie       },
     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
-    [CSR_HGEIP]       = { "hgeip",       hmode,   read_hgeip,       write_hgeip       },
+    [CSR_HGEIP]       = { "hgeip",       hmode,   read_zero,        write_hgeip       },
     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },