diff mbox series

[v5,16/24] target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation

Message ID 20210823195529.560295-17-richard.henderson@linaro.org
State Accepted
Commit 33979526cad412b72afd1989a22dcd218b2ce170
Headers show
Series target/riscv: Use tcg_constant_* | expand

Commit Message

Richard Henderson Aug. 23, 2021, 7:55 p.m. UTC 
We distinguish write-only by passing ret_value as NULL.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/riscv/csr.c | 23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)

-- 
2.25.1

Comments

Bin Meng Aug. 24, 2021, 6:37 a.m. UTC | #1 
On Tue, Aug 24, 2021 at 4:02 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> We distinguish write-only by passing ret_value as NULL.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/riscv/csr.c | 23 +++++++++++++++--------

>  1 file changed, 15 insertions(+), 8 deletions(-)

>


Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Alistair Francis Aug. 25, 2021, 6:08 a.m. UTC | #2 
On Tue, Aug 24, 2021 at 6:03 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> We distinguish write-only by passing ret_value as NULL.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Alistair Francis <alistair.francis@wdc.com>


Alistair

> ---

>  target/riscv/csr.c | 23 +++++++++++++++--------

>  1 file changed, 15 insertions(+), 8 deletions(-)

>

> diff --git a/target/riscv/csr.c b/target/riscv/csr.c

> index 9a4ed18ac5..d900f96dc1 100644

> --- a/target/riscv/csr.c

> +++ b/target/riscv/csr.c

> @@ -937,9 +937,12 @@ static RISCVException rmw_vsip(CPURISCVState *env, int csrno,

>      /* Shift the S bits to their VS bit location in mip */

>      int ret = rmw_mip(env, 0, ret_value, new_value << 1,

>                        (write_mask << 1) & vsip_writable_mask & env->hideleg);

> -    *ret_value &= VS_MODE_INTERRUPTS;

> -    /* Shift the VS bits to their S bit location in vsip */

> -    *ret_value >>= 1;

> +

> +    if (ret_value) {

> +        *ret_value &= VS_MODE_INTERRUPTS;

> +        /* Shift the VS bits to their S bit location in vsip */

> +        *ret_value >>= 1;

> +    }

>      return ret;

>  }

>

> @@ -956,7 +959,9 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,

>                        write_mask & env->mideleg & sip_writable_mask);

>      }

>

> -    *ret_value &= env->mideleg;

> +    if (ret_value) {

> +        *ret_value &= env->mideleg;

> +    }

>      return ret;

>  }

>

> @@ -1072,8 +1077,9 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno,

>      int ret = rmw_mip(env, 0, ret_value, new_value,

>                        write_mask & hvip_writable_mask);

>

> -    *ret_value &= hvip_writable_mask;

> -

> +    if (ret_value) {

> +        *ret_value &= hvip_writable_mask;

> +    }

>      return ret;

>  }

>

> @@ -1084,8 +1090,9 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,

>      int ret = rmw_mip(env, 0, ret_value, new_value,

>                        write_mask & hip_writable_mask);

>

> -    *ret_value &= hip_writable_mask;

> -

> +    if (ret_value) {

> +        *ret_value &= hip_writable_mask;

> +    }

>      return ret;

>  }

>

> --

> 2.25.1

>

>
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9a4ed18ac5..d900f96dc1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -937,9 +937,12 @@  static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
     /* Shift the S bits to their VS bit location in mip */
     int ret = rmw_mip(env, 0, ret_value, new_value << 1,
                       (write_mask << 1) & vsip_writable_mask & env->hideleg);
-    *ret_value &= VS_MODE_INTERRUPTS;
-    /* Shift the VS bits to their S bit location in vsip */
-    *ret_value >>= 1;
+
+    if (ret_value) {
+        *ret_value &= VS_MODE_INTERRUPTS;
+        /* Shift the VS bits to their S bit location in vsip */
+        *ret_value >>= 1;
+    }
     return ret;
 }
 
@@ -956,7 +959,9 @@  static RISCVException rmw_sip(CPURISCVState *env, int csrno,
                       write_mask & env->mideleg & sip_writable_mask);
     }
 
-    *ret_value &= env->mideleg;
+    if (ret_value) {
+        *ret_value &= env->mideleg;
+    }
     return ret;
 }
 
@@ -1072,8 +1077,9 @@  static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
     int ret = rmw_mip(env, 0, ret_value, new_value,
                       write_mask & hvip_writable_mask);
 
-    *ret_value &= hvip_writable_mask;
-
+    if (ret_value) {
+        *ret_value &= hvip_writable_mask;
+    }
     return ret;
 }
 
@@ -1084,8 +1090,9 @@  static RISCVException rmw_hip(CPURISCVState *env, int csrno,
     int ret = rmw_mip(env, 0, ret_value, new_value,
                       write_mask & hip_writable_mask);
 
-    *ret_value &= hip_writable_mask;
-
+    if (ret_value) {
+        *ret_value &= hip_writable_mask;
+    }
     return ret;
 }