mbox series

[v6,0/3] Add L3 provider support for SC7280

Message ID 1628577962-3995-1-git-send-email-okukatla@codeaurora.org
Headers show
Series Add L3 provider support for SC7280 | expand

Message

Odelu Kukatla Aug. 10, 2021, 6:45 a.m. UTC 
Add Epoch Subsystem (EPSS) L3 provider support on SM7280 SoCs.

v6:
 - Addressed review comments(v5) and added a chage missed in v5.
 
Depends on: https://lore.kernel.org/patchwork/patch/1466834/

Odelu Kukatla (3):
  dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280
  interconnect: qcom: Add EPSS L3 support on SC7280
  arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

 .../bindings/interconnect/qcom,osm-l3.yaml         |   9 +-
 arch/arm64/boot/dts/qcom/sc7280.dtsi               |   9 ++
 drivers/interconnect/qcom/osm-l3.c                 | 136 +++++++++++++++++----
 drivers/interconnect/qcom/sc7280.h                 |  10 ++
 include/dt-bindings/interconnect/qcom,osm-l3.h     |  10 +-
 5 files changed, 151 insertions(+), 23 deletions(-)

Comments

Georgi Djakov Aug. 10, 2021, 12:33 p.m. UTC | #1 
Hi Odelu,

On 10.08.21 9:46, Odelu Kukatla wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
> SoCs.
> 
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> ---
>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++
>   1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 53a21d0..e78f055 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -586,6 +586,15 @@
>   			qcom,bcm-voters = <&apps_bcm_voter>;
>   		};
>   
> +		epss_l3: interconnect@18590000 {

This DT node should be moved after apps_rsc: rsc@18200000
and before cpufreq@18591000

> +			compatible = "qcom,sc7280-epss-l3";
> +			reg = <0 0x18590000 0 1000>, <0 0x18591000 0 0x100>,
> +				<0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>;

Please align to the open parenthesis, to be consistent with the rest of
the file.

> +			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> +			clock-names = "xo", "alternate";
> +			#interconnect-cells = <1>;
> +		};
> +
>   		ipa: ipa@1e40000 {
>   			compatible = "qcom,sc7280-ipa";

Thanks,
Georgi
Odelu Kukatla Aug. 16, 2021, 5:44 p.m. UTC | #2 
On 2021-08-10 18:03, Georgi Djakov wrote:
> Hi Odelu,
> 
> On 10.08.21 9:46, Odelu Kukatla wrote:
>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
>> SoCs.
>> 
>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
>> ---
>>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 53a21d0..e78f055 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -586,6 +586,15 @@
>>   			qcom,bcm-voters = <&apps_bcm_voter>;
>>   		};
>>   +		epss_l3: interconnect@18590000 {
> 
> This DT node should be moved after apps_rsc: rsc@18200000
> and before cpufreq@18591000
> 
Thanks for review! will address this in next revision.
>> +			compatible = "qcom,sc7280-epss-l3";
>> +			reg = <0 0x18590000 0 1000>, <0 0x18591000 0 0x100>,
>> +				<0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>;
> 
> Please align to the open parenthesis, to be consistent with the rest of
> the file.
> 
will address this in next revision.
>> +			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
>> +			clock-names = "xo", "alternate";
>> +			#interconnect-cells = <1>;
>> +		};
>> +
>>   		ipa: ipa@1e40000 {
>>   			compatible = "qcom,sc7280-ipa";
> 
> Thanks,
> Georgi
Sibi Sankar Aug. 16, 2021, 6:09 p.m. UTC | #3 
Hey Odelu,
Thanks for the patch.

On 2021-08-10 12:16, Odelu Kukatla wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280
> SoCs.
> 
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> ---
>  .../devicetree/bindings/interconnect/qcom,osm-l3.yaml          |  9 
> ++++++++-
>  include/dt-bindings/interconnect/qcom,osm-l3.h                 | 10 
> +++++++++-
>  2 files changed, 17 insertions(+), 2 deletions(-)
> 
> diff --git
> a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> index e701524..919fce4 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> @@ -18,13 +18,20 @@ properties:
>    compatible:
>      enum:
>        - qcom,sc7180-osm-l3
> +      - qcom,sc7280-epss-l3
>        - qcom,sc8180x-osm-l3
>        - qcom,sdm845-osm-l3
>        - qcom,sm8150-osm-l3
>        - qcom,sm8250-epss-l3
> 
>    reg:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 4
> +    items:
> +      - description: OSM clock domain-0 base address and size
> +      - description: OSM clock domain-1 base address and size
> +      - description: OSM clock domain-2 base address and size
> +      - description: OSM clock domain-3 base address and size

Looks like you missed addressing
Stephen's comment from v4 i.e.
having descriptions based on
compatibles.

> 
>    clocks:
>      items:
> diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h
> b/include/dt-bindings/interconnect/qcom,osm-l3.h
> index 61ef649..99534a5 100644
> --- a/include/dt-bindings/interconnect/qcom,osm-l3.h
> +++ b/include/dt-bindings/interconnect/qcom,osm-l3.h
> @@ -1,6 +1,6 @@
>  /* SPDX-License-Identifier: GPL-2.0 */
>  /*
> - * Copyright (C) 2019 The Linux Foundation. All rights reserved.
> + * Copyright (C) 2019, 2021 The Linux Foundation. All rights reserved.
>   */
> 
>  #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
> @@ -11,5 +11,13 @@
> 
>  #define MASTER_EPSS_L3_APPS	0
>  #define SLAVE_EPSS_L3_SHARED	1
> +#define SLAVE_EPSS_L3_CPU0	2
> +#define SLAVE_EPSS_L3_CPU1	3
> +#define SLAVE_EPSS_L3_CPU2	4
> +#define SLAVE_EPSS_L3_CPU3	5
> +#define SLAVE_EPSS_L3_CPU4	6
> +#define SLAVE_EPSS_L3_CPU5	7
> +#define SLAVE_EPSS_L3_CPU6	8
> +#define SLAVE_EPSS_L3_CPU7	9
> 
>  #endif