diff mbox series

[v5,4/6] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support

Message ID 20210727185527.19907-5-biju.das.jz@bp.renesas.com
State Superseded
Headers show
Series None | expand

Commit Message

Biju Das July 27, 2021, 6:55 p.m. UTC 
Add USB2.0 phy and host support to SoC DT.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v4->v5:
 * No change.
V3->v4:
 * Removed second reset from phy node.
 V3:
  * Added reset entries
  * Updated compatible, phy and reset entries.
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 94 ++++++++++++++++++++++
 1 file changed, 94 insertions(+)

Comments

Geert Uytterhoeven Aug. 10, 2021, 10:19 a.m. UTC | #1 
Hi Biju,

On Tue, Jul 27, 2021 at 8:55 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add USB2.0 phy and host support to SoC DT.

>

> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>


Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi

> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi

> @@ -200,6 +200,100 @@

>                               <0x0 0x11940000 0 0x60000>;

>                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;

>                 };

> +

> +               phyrst: usbphy-ctrl@11c40000 {

> +                       compatible = "renesas,r9a07g044-usbphy-ctrl",

> +                                    "renesas,rzg2l-usbphy-ctrl";

> +                       reg = <0 0x11c40000 0 0x10000>;

> +                       clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;

> +                       resets = <&cpg R9A07G044_USB_PRESETN>;

> +                       power-domains = <&cpg>;

> +                       #reset-cells = <1>;


Should there be a status = "disabled"?

> +               };


The rest looks good to me, so with the above clarified:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>


Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Biju Das Aug. 12, 2021, 7:17 a.m. UTC | #2 
Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v5 4/6] arm64: dts: renesas: r9a07g044: Add USB2.0 phy

> and host support

> 

> Hi Biju,

> 

> On Tue, Jul 27, 2021 at 8:55 PM Biju Das <biju.das.jz@bp.renesas.com>

> wrote:

> > Add USB2.0 phy and host support to SoC DT.

> >

> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> 

> Thanks for your patch!

> 

> > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi

> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi

> > @@ -200,6 +200,100 @@

> >                               <0x0 0x11940000 0 0x60000>;

> >                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;

> >                 };

> > +

> > +               phyrst: usbphy-ctrl@11c40000 {

> > +                       compatible = "renesas,r9a07g044-usbphy-ctrl",

> > +                                    "renesas,rzg2l-usbphy-ctrl";

> > +                       reg = <0 0x11c40000 0 0x10000>;

> > +                       clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;

> > +                       resets = <&cpg R9A07G044_USB_PRESETN>;

> > +                       power-domains = <&cpg>;

> > +                       #reset-cells = <1>;

> 

> Should there be a status = "disabled"?


OK, will add it in SoC dtsi, since all RZ/G2L based boards have USB support.

In future, if there is a requirement for handling of permanently unused pin
as mentioned in section "34.4.2. Handling of permanently unused pin"
then we need to enable this driver in SoC dtsi. with dt-binding and driver probe 
changes for handling the same.

Cheers,
Biju

> 

> > +               };

> 

> The rest looks good to me, so with the above clarified:

> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

> 

> Gr{oetje,eeting}s,

> 

>                         Geert

> 

> --

> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-

> m68k.org

> 

> In personal conversations with technical people, I call myself a hacker.

> But when I'm talking to journalists I just say "programmer" or something

> like that.

>                                 -- Linus Torvalds
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 9a7489dc70d1..f0dcd086ba20 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -200,6 +200,100 @@ 
 			      <0x0 0x11940000 0 0x60000>;
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 		};
+
+		phyrst: usbphy-ctrl@11c40000 {
+			compatible = "renesas,r9a07g044-usbphy-ctrl",
+				     "renesas,rzg2l-usbphy-ctrl";
+			reg = <0 0x11c40000 0 0x10000>;
+			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+			resets = <&cpg R9A07G044_USB_PRESETN>;
+			power-domains = <&cpg>;
+			#reset-cells = <1>;
+		};
+
+		ohci0: usb@11c50000 {
+			compatible = "generic-ohci";
+			reg = <0 0x11c50000 0 0x100>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+				 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+			resets = <&phyrst 0>,
+				 <&cpg R9A07G044_USB_U2H0_HRESETN>;
+			phys = <&usb2_phy0 1>;
+			phy-names = "usb";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ohci1: usb@11c70000 {
+			compatible = "generic-ohci";
+			reg = <0 0x11c70000 0 0x100>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+				 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+			resets = <&phyrst 1>,
+				 <&cpg R9A07G044_USB_U2H1_HRESETN>;
+			phys = <&usb2_phy1 1>;
+			phy-names = "usb";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ehci0: usb@11c50100 {
+			compatible = "generic-ehci";
+			reg = <0 0x11c50100 0 0x100>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+				 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+			resets = <&phyrst 0>,
+				 <&cpg R9A07G044_USB_U2H0_HRESETN>;
+			phys = <&usb2_phy0 2>;
+			phy-names = "usb";
+			companion = <&ohci0>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ehci1: usb@11c70100 {
+			compatible = "generic-ehci";
+			reg = <0 0x11c70100 0 0x100>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+				 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+			resets = <&phyrst 1>,
+				 <&cpg R9A07G044_USB_U2H1_HRESETN>;
+			phys = <&usb2_phy1 2>;
+			phy-names = "usb";
+			companion = <&ohci1>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		usb2_phy0: usb-phy@11c50200 {
+			compatible = "renesas,usb2-phy-r9a07g044",
+				     "renesas,rzg2l-usb2-phy";
+			reg = <0 0x11c50200 0 0x700>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+				 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+			resets = <&phyrst 0>;
+			#phy-cells = <1>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		usb2_phy1: usb-phy@11c70200 {
+			compatible = "renesas,usb2-phy-r9a07g044",
+				     "renesas,rzg2l-usb2-phy";
+			reg = <0 0x11c70200 0 0x700>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+				 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+			resets = <&phyrst 1>;
+			#phy-cells = <1>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
 	};
 
 	timer {